diff options
| author | Valentin Raevsky <valentin@compulab.co.il> | 2019-02-19 11:50:09 +0200 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2020-02-06 15:00:36 +0100 |
| commit | 8a9e44182e2b8319f6c0c8824af2d3bff1d4c381 (patch) | |
| tree | 8ca00053dce2e342b2700e55954f73de99ce54a7 /drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h | |
| parent | 9c623983abc48e9cf9d366900c50428e119e5f63 (diff) | |
sn65dsi83: Add ti,sn65dsi83 dsi to lvds bridge driver
Related-to: ELB-2289
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h')
| -rw-r--r-- | drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h b/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h new file mode 100644 index 000000000000..e9bb6633c376 --- /dev/null +++ b/drivers/gpu/drm/bridge/sn65dsi83/sn65dsi83_timing.h @@ -0,0 +1,33 @@ +#ifndef __SN65DSI83_TIMING_H__ +#define __SN65DSI83_TIMING_H__ + +/* Default Video Parameters */ +#define PIXCLK_INIT 62500000 + +#define HACTIVE_INIT 1280 +#define HPW_INIT 2 +#define HBP_INIT 6 +#define HFP_INIT 5 + +#define VACTIVE_INIT 800 +#define VPW_INIT 1 +#define VBP_INIT 2 +#define VFP_INIT 3 + +static const struct display_timing panel_default_timing = { + .pixelclock = { PIXCLK_INIT, PIXCLK_INIT, PIXCLK_INIT }, + .hactive = { HACTIVE_INIT, HACTIVE_INIT, HACTIVE_INIT }, + .hfront_porch = { HFP_INIT, HFP_INIT, HFP_INIT }, + .hsync_len = { HPW_INIT, HPW_INIT, HPW_INIT }, + .hback_porch = { HBP_INIT, HBP_INIT, HBP_INIT }, + .vactive = { VACTIVE_INIT, VACTIVE_INIT, VACTIVE_INIT }, + .vfront_porch = { VFP_INIT, VFP_INIT, VFP_INIT }, + .vsync_len = { VPW_INIT, VPW_INIT, VPW_INIT }, + .vback_porch = { VBP_INIT, VBP_INIT, VBP_INIT }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | + DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW | + DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + +#endif /* __SN65DSI83_TIMING_H__ */ |