diff options
| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-07-24 17:18:06 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-07-25 07:30:41 +0100 |
| commit | 702668e606c0618fd62c7a5d051c9faee256c049 (patch) | |
| tree | cc3bea68c9875df70d8d6d962202c8804083eaa5 /drivers/gpu/drm/i915/i915_irq.c | |
| parent | 2bf8fb39eb70b6cf1d0f7efbe9fa9fb27d55fdf4 (diff) | |
drm/i915/uc: Unify uC platform check
We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace all the checks with a unified
HAS_UC.
v2: use HAS_GT_UC (Michal)
v3: fix comment (Michal)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190725001813.4740-2-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 11c73af92597..a17d4fd17962 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4766,7 +4766,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev_priv->l3_parity.remap_info[i] = NULL; /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ - if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11) + if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; /* Let's track the enabled rps events */ |