diff options
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-03-10 12:18:34 +0200 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-03-14 16:07:00 +0200 |
| commit | 3465dbddf07084b36cd36c1f5f25b1734b85eff4 (patch) | |
| tree | c33ca36b9a5856300572768e816eafbfdefb7abd /drivers/gpu/drm/i915/intel_color.c | |
| parent | 7d2ec88149926b7ad875b9f95595e763e43d6105 (diff) | |
drm/i915/glk: Improve rounding caused by pre-CSC gamma tables
The 33rd entry in the pre-CSC gamma table in Geminilake can represent a
value of 1.0 as 17 bits fixed point with one integer bit. However, the
table was generated such that the value of 1.0 would be 0.ffff with
all the intervals scaled accordingly. For instance, 0.5 mapped to
0.7fff instead of 0.8000.
For a reason that is not clear to the author, the rounding seems to be
different when a cursor plane is used, leading to some seemingly random
failures of the kms_cursor_crc igt tests. The differences weren't
perceptible at 8bpc with images captured by a Chamelium device, but did
cause CRC mismatches.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170310101835.29845-1-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_color.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index b9e5266d933b..306c6b06b330 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -465,14 +465,14 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state) * different values per channel, so this just loads a linear table. */ for (i = 0; i < lut_size; i++) { - uint32_t v = (i * ((1 << 16) - 1)) / (lut_size - 1); + uint32_t v = (i * (1 << 16)) / (lut_size - 1); I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); } /* Clamp values > 1.0. */ while (i++ < 35) - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16) - 1); + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); } static void glk_load_luts(struct drm_crtc_state *state) |