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author | Otavio Salvador <otavio@ossystems.com.br> | 2019-03-28 10:47:24 -0300 |
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committer | GitHub <noreply@github.com> | 2019-03-28 10:47:24 -0300 |
commit | 0a8ab17689e628c84a666195bfc6ab85d11cf057 (patch) | |
tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /drivers/gpu/drm/i915/intel_lrc.c | |
parent | 1e71d8c630cbc0d1f5d762fd019690b5cdb880ae (diff) | |
parent | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (diff) |
Merge pull request #46 from toradex/4.9-2.3.x-imx
4.9 2.3.x imx
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fd11be6b23b9..62bcc770a181 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -386,8 +386,13 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq) * may not be visible to the HW prior to the completion of the UC * register write and that we may begin execution from the context * before its image is complete leading to invalid PD chasing. + * + * Furthermore, Braswell, at least, wants a full mb to be sure that + * the writes are coherent in memory (visible to the GPU) prior to + * execution, and not just visible to other CPUs (as is the result of + * wmb). */ - wmb(); + mb(); return ce->lrc_desc; } |