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authorEric Anholt <eric@anholt.net>2011-05-06 13:55:53 -0700
committerKeith Packard <keithp@keithp.com>2011-05-13 18:12:51 -0700
commit25aebfc30bc40f01813aad7a0f62f2fda44efb8a (patch)
tree254e17372e55ed02ecec961f95ab37f07b5c9e23 /drivers/gpu/drm/i915
parent10ed13e4a5143000bca816982ea6e68e2a4ac050 (diff)
drm/i915: Add support for fence registers on Ivybridge.
The registers are the same as on Sandybridge. Fixes scrambled display in X when it does software drawing to the GTT, and scans the results out as tiled. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4304f74dfb5f..c6289034e29a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2673,6 +2673,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
update:
obj->tiling_changed = false;
switch (INTEL_INFO(dev)->gen) {
+ case 7:
case 6:
ret = sandybridge_write_fence_reg(obj, pipelined);
break;
@@ -2706,6 +2707,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
uint32_t fence_reg = reg - dev_priv->fence_regs;
switch (INTEL_INFO(dev)->gen) {
+ case 7:
case 6:
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
break;