diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-12-10 12:46:49 +0200 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:59:03 +0800 |
| commit | 37d8088c18902c24ed471f28f77fe62813d782f5 (patch) | |
| tree | 3993a75a580b4e8c83076595ba95bd16f50ea09f /drivers/gpu/drm/mxsfb/mxsfb_crtc.c | |
| parent | b53ccc9cba83e98c3b01789d52d122b3f1fbae2d (diff) | |
drm/mxsfb: Clear OUTSTANDING_REQS bits
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF
is enabled, since it comes up with default value of 1 (this behaviour
has been seen on some imx8 platforms).
In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting
its value.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Guido Günther <agx@sigxcpu.org>
Diffstat (limited to 'drivers/gpu/drm/mxsfb/mxsfb_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index e727f5e11f89..a12f53d63d7d 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -225,6 +225,13 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) clk_prepare_enable(mxsfb->clk); if (mxsfb->devdata->ipversion >= 4) { + /* + * On some platforms, bit 21 is defaulted to 1, which may alter + * the below setting. So, to make sure we have the right setting + * clear all the bits for CTRL2_OUTSTANDING_REQS. + */ + writel(CTRL2_OUTSTANDING_REQS(0x7), + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR); writel(CTRL2_OUTSTANDING_REQS(REQ_16), mxsfb->base + LCDC_V4_CTRL2 + REG_SET); /* Assert LCD Reset bit */ |