diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-05-07 16:58:27 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-05-18 18:21:53 +1000 |
| commit | ce8a3eb20c4cb7d9e0c33e7560070688cd9066fc (patch) | |
| tree | d4d643a97c733ac67a3ab9c356a3b1506b73b8a4 /drivers/gpu/drm/radeon/r100.c | |
| parent | ce8f53709bf440100cb9d31b1303291551cf517f (diff) | |
drm/radeon/kms/pm: make pm spam debug only
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 4c5d21bfa2c4..9a59ba46f078 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -141,13 +141,13 @@ void r100_pm_get_dynpm_state(struct radeon_device *rdev) /* only one clock mode per power state */ rdev->pm.requested_clock_mode_index = 0; - DRM_INFO("Requested: e: %d m: %d p: %d\n", - rdev->pm.power_state[rdev->pm.requested_power_state_index]. - clock_info[rdev->pm.requested_clock_mode_index].sclk, - rdev->pm.power_state[rdev->pm.requested_power_state_index]. - clock_info[rdev->pm.requested_clock_mode_index].mclk, - rdev->pm.power_state[rdev->pm.requested_power_state_index]. - pcie_lanes); + DRM_DEBUG("Requested: e: %d m: %d p: %d\n", + rdev->pm.power_state[rdev->pm.requested_power_state_index]. + clock_info[rdev->pm.requested_clock_mode_index].sclk, + rdev->pm.power_state[rdev->pm.requested_power_state_index]. + clock_info[rdev->pm.requested_clock_mode_index].mclk, + rdev->pm.power_state[rdev->pm.requested_power_state_index]. + pcie_lanes); } void r100_pm_init_profile(struct radeon_device *rdev) @@ -266,7 +266,7 @@ void r100_pm_misc(struct radeon_device *rdev) rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { radeon_set_pcie_lanes(rdev, ps->pcie_lanes); - DRM_INFO("Setting: p: %d\n", ps->pcie_lanes); + DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); } } |