diff options
| author | Sandarbh Jain <sanjain@nvidia.com> | 2015-06-12 00:45:02 +0530 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2015-06-12 17:10:40 -0700 |
| commit | 01e2315df5aeadd04124b55551539280e4387f45 (patch) | |
| tree | e8682ae6f3210fef803e2c9f9fc823083fb20122 /drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |
| parent | b1de4caf2f12e1bc9c3a4e08dd60b5de53b7520a (diff) | |
gpu: nvgpu: Disable channel when updating SMPC WAR
When updating SMPC WAR for channel, it needs to be kicked out. This
ensures that the updated information is re-read from context header.
Bug 1579548
Change-Id: Ieadc6b65b057d7f48dc16fbc786c881ab7e5fcd5
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: http://git-master/r/756639
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
| -rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 07137c28ea6e..755fcdda5742 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -3,7 +3,7 @@ * * GK20A Graphics channel * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -418,6 +418,23 @@ void gk20a_disable_channel_no_update(struct channel_gk20a *ch) ccsr_channel_enable_clr_true_f()); } +static void channel_gk20a_enable(struct channel_gk20a *ch) +{ + /* enable channel */ + gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), + gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | + ccsr_channel_enable_set_true_f()); +} + +static void channel_gk20a_disable(struct channel_gk20a *ch) +{ + /* disable channel */ + gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), + gk20a_readl(ch->g, + ccsr_channel_r(ch->hw_chid)) | + ccsr_channel_enable_clr_true_f()); +} + int gk20a_wait_channel_idle(struct channel_gk20a *ch) { bool channel_idle = false; @@ -1939,6 +1956,8 @@ clean_up: void gk20a_init_channel(struct gpu_ops *gops) { gops->fifo.bind_channel = channel_gk20a_bind; + gops->fifo.disable_channel = channel_gk20a_disable; + gops->fifo.enable_channel = channel_gk20a_enable; } long gk20a_channel_ioctl(struct file *filp, |