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| author | Thierry Reding <treding@nvidia.com> | 2014-11-07 16:10:41 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-05-04 12:54:23 +0200 |
| commit | 242b1d713386e8e2fd7f62cc1ed4681a12290848 (patch) | |
| tree | e91adedcd99c0700c64e53bc4fa72117e7ade8ef /drivers/memory/tegra/mc.c | |
| parent | d1313e7896e932a92e21912850ef034e58571b66 (diff) | |
memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/mc.c')
| -rw-r--r-- | drivers/memory/tegra/mc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index fe3c44e7e1d1..9b7c1645fd59 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -58,6 +58,9 @@ static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, #endif +#ifdef CONFIG_ARCH_TEGRA_132_SOC + { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, +#endif { } }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); |