diff options
| author | Aisheng.Dong <b29396@freescale.com> | 2010-09-27 13:31:08 +0800 |
|---|---|---|
| committer | Aisheng.Dong <b29396@freescale.com> | 2010-09-27 15:53:29 +0800 |
| commit | 89f0eb77382692c0774c0eae57e6b4f8862e756d (patch) | |
| tree | 49a34658a7a1ae65e7a64b58b3529ffd3f4d6bb9 /drivers/mmc | |
| parent | 0165c042aeb22bc03a3e833de5f316a39bdbe92c (diff) | |
ENGR00131968 esdhc: fix esdhc gets CRC errors when AHB is 24Mhz
This issue is found on MX50 ARM2 board when AHB is 24Mhz and esdhc
is 50Mhz (maybe just need > 24Mhz, however not tested).
We found it's related to the clock auto gate function of esdhc which
enables the controller to automatically gate on/off the required clocks
based on its internal logic judgement.
After disabling clock auto gate function, we could not reproduce it anymore.
Thus we disable clock auto gate here to get better compatibility.
It could be regarded as a workaround due to it may be h/w bug of auto gate
of esdhc(not confirmed).
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/mx_sdhci.c | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c index 8f81a40fae27..5df8c31c405e 100644 --- a/drivers/mmc/host/mx_sdhci.c +++ b/drivers/mmc/host/mx_sdhci.c @@ -435,9 +435,6 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) host->data = data; host->data_early = 0; - if (host->data->flags & MMC_DATA_READ) - writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL) | - SDHCI_CLOCK_HLK_EN, host->ioaddr + SDHCI_CLOCK_CONTROL); /* timeout in us */ target_timeout = data->timeout_ns / 1000 + @@ -853,13 +850,9 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div); clk |= (prescaler << 8) | (div << 4); - if (host->plat_data->clk_always_on - | (host->mmc->card && mmc_card_sdio(host->mmc->card))) - clk |= SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN - | SDHCI_CLOCK_IPG_EN; - else - clk &= ~(SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN - | SDHCI_CLOCK_IPG_EN); + /* Disable clock auto gate to get better compatibility */ + clk |= SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN + | SDHCI_CLOCK_IPG_EN; /* Configure the clock delay line */ if ((host->plat_data->vendor_ver >= ESDHC_VENDOR_V3) @@ -1417,10 +1410,6 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) host->ioaddr + SDHCI_DMA_ADDRESS); if (intmask & SDHCI_INT_DATA_END) { - if (host->data->flags & MMC_DATA_READ) - writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL) - & ~SDHCI_CLOCK_HLK_EN, - host->ioaddr + SDHCI_CLOCK_CONTROL); if (host->cmd) { /* * Data managed to finish before the |