diff options
| author | Jason Chen <b02280@freescale.com> | 2009-12-16 15:32:32 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2010-03-25 14:01:46 -0400 |
| commit | 4b4cc7389a84a3e6c79586a7b65a218a5401d11a (patch) | |
| tree | d98af9307e47a1c65bbf6e9877a9397ee167eb45 /drivers/mxc/ipu3/ipu_common.c | |
| parent | acc41cfb94eece13a5d2b9dca2543885f6211a8f (diff) | |
ENGR00119275 ipuv3: dmfc size control
add dmfc size control for dynamic change and _setup.
DMFC_NORMAL: segment 0,1 for DC, 4,5 for DP-BG, 6,7 for DP-FG.
DMFC_HIGH_RESOLUTION_DC: segment 0~3 for DC, 4,5 for DP-BG, 6,7 for DP-FG.
DMFC_HIGH_RESOLUTION_DP: segment 0,1 for DC, 2~5 for DP-BG, 6,7 for DP-FG.
DMFC_HIGH_RESOLUTION_ONLY_DP: segment 0~3 for DP-BG, 4~7 for DP-FG.
IPU diplay driver will try to enlarge its related DMFC segment size
when it meet high resolution condition, but if dmfc is already in high
resolution setting, dmfc will not change.That said, first request wins.
For cmdline setting, "dmfc=1" is DMFC_HIGH_RESOLUTION_DC, "dmfc=2"
is DMFC_HIGH_RESOLUTION_DP, "dmfc=3" is
DMFC_HIGH_RESOLUTION_ONLY_DP.
NOTE: DMFC_HIGH_RESOLUTION_ONLY_DP only can be set by cmdline.
Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'drivers/mxc/ipu3/ipu_common.c')
| -rw-r--r-- | drivers/mxc/ipu3/ipu_common.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 56657b8f6ea1..16e7f01605fb 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -278,7 +278,6 @@ static int ipu_probe(struct platform_device *pdev) struct resource *res; struct mxc_ipu_config *plat_data = pdev->dev.platform_data; unsigned long ipu_base; - u32 reg; spin_lock_init(&ipu_lock); @@ -379,7 +378,7 @@ static int ipu_probe(struct platform_device *pdev) __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10)); /* DMFC Init */ - _ipu_dmfc_init(); + _ipu_dmfc_init(DMFC_NORMAL, 1); /* Set sync refresh channels as high priority */ __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); @@ -2407,7 +2406,7 @@ static int ipu_resume(struct platform_device *pdev) __raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32)); } else { clk_enable(g_ipu_clk); - _ipu_dmfc_init(); + _ipu_dmfc_init(DMFC_NORMAL, 0); _ipu_init_dc_mappings(); /* Set sync refresh channels as high priority */ |