diff options
| author | Divy Le Ray <divy@chelsio.com> | 2009-07-30 21:23:39 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-08-02 12:23:40 -0700 |
| commit | 88e7b76ef7cf939a0cf23a1902030211b20837fe (patch) | |
| tree | 7bfd1742802e9cdb5539a0320f2440b524a3f71e /drivers/net/cxgb3/t3_hw.c | |
| parent | 9450526ac7bd74edf1ee030841d8078c6db6ca0b (diff) | |
cxgb3: fix Gen2 pci default settings
Modify control register settings to accommodate the bridge's max read
requset size.
Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/cxgb3/t3_hw.c')
| -rw-r--r-- | drivers/net/cxgb3/t3_hw.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c index e78d341cbd60..526e144b8b74 100644 --- a/drivers/net/cxgb3/t3_hw.c +++ b/drivers/net/cxgb3/t3_hw.c @@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap) {201, 321, 258, 450, 834, 1602} }; - u16 val; + u16 val, devid; unsigned int log2_width, pldsize; unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; @@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap) adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, &val); pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; + + pci_read_config_word(adap->pdev, 0x2, &devid); + if (devid == 0x37) { + pci_write_config_word(adap->pdev, + adap->params.pci.pcie_cap_addr + + PCI_EXP_DEVCTL, + val & ~PCI_EXP_DEVCTL_READRQ & + ~PCI_EXP_DEVCTL_PAYLOAD); + pldsize = 0; + } + pci_read_config_word(adap->pdev, adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, &val); |