diff options
| author | Shiju Jose <shiju.jose@huawei.com> | 2018-10-19 20:15:32 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-22 19:31:14 -0700 |
| commit | 01865a50d78f515423422b8c55e8b6f6bf4c2cd4 (patch) | |
| tree | 56ab75dc4b1007beae67d3f0f650504c1407d7ce /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | |
| parent | da2d072a9ea75dd5babebcfd71144fb5b3aa9913 (diff) | |
net: hns3: Add enable and process hw errors of TM scheduler
This patch enables and process hw errors of TM scheduler and
QCN(Quantized Congestion Control).
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index c6d373929be6..e0e3b5861495 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -37,6 +37,8 @@ #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F +#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3 +#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF #define HCLGE_NCSI_ERR_INT_EN 0x3 #define HCLGE_NCSI_ERR_INT_TYPE 0x9 @@ -76,5 +78,6 @@ struct hclge_hw_error { }; int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); +int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en); pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev); #endif |