diff options
| author | Shiju Jose <shiju.jose@huawei.com> | 2018-10-19 20:15:30 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-22 19:31:13 -0700 |
| commit | bf1faf9415ddbfaa6d6a56a4bc594c92ca0f7309 (patch) | |
| tree | fcc4f02b3c20daf88fd795386f9fd0346fe98d74 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | |
| parent | 6d67ee9a273bbb5d3f7d66eedb924aee21c2b2cd (diff) | |
net: hns3: Add enable and process hw errors from IGU, EGU and NCSI
This patch adds enable and processing of hw errors from IGU(Ingress Unit),
EGU(Egress Unit) and NCSI(Network Controller Sideband Interface).
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index b413141085a5..f46c8c29a17e 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -23,6 +23,12 @@ #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF +#define HCLGE_IGU_ERR_INT_EN 0x0000066F +#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F +#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF +#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F +#define HCLGE_NCSI_ERR_INT_EN 0x3 +#define HCLGE_NCSI_ERR_INT_TYPE 0x9 #define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF #define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3 @@ -35,6 +41,8 @@ #define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF #define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000 #define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001 +#define HCLGE_IGU_COM_INT_MASK 0xF +#define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F enum hclge_err_int_type { HCLGE_ERR_INT_MSIX = 0, |