diff options
| author | Salil Mehta <salil.mehta@huawei.com> | 2018-12-07 21:08:06 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-12-07 15:57:01 -0800 |
| commit | f6162d44126ce0f601f92afc770648b73924eb6c (patch) | |
| tree | e711b712327ea13fffb0f0b60123b789be5896af /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | |
| parent | 8bb147927c7c6caf8a26d9f5022f5744b12ea55a (diff) | |
net: hns3: add handling of hw errors reported through MSIX
This patch adds handling for HNS3 hardware errors(non-standard)
which are reported through MSIX interrupts and not through
PCIe AER channel.
These MSIX reported hardware errors are handled using common
misc. interrupt handler. Hardware error related registers
cannot be cleared in context to the interrupt received as
they require *heavy* access to hardware using IMP(Integrated
Mangement Processor) commands. Hence, we defer the clearing
of such error events till later time.
Since, we have defered exact identification of errors we
will have to defer the level of receovery/reset which
might be required. Hence, a new reset type UNKNOWN reset
has been introduced which effectively defers the assertion
of the reset till we get hold of kind of errors at later
time.
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index 809e6981aa8b..05adccbd04ab 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -9,6 +9,9 @@ #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 #define HCLGE_RAS_REG_NFE_MASK 0xFF00 +#define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800 +#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00 + #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300 @@ -69,4 +72,6 @@ struct hclge_hw_error { int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev); +int hclge_handle_hw_msix_error(struct hclge_dev *hdev, + unsigned long *reset_requests); #endif |