diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-25 10:08:16 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-08-26 15:47:53 -0700 |
| commit | e7126997342560533317d8467e8516119ebcbd21 (patch) | |
| tree | cc592fc98d946756caa30dd6dccde7374d3af2e4 /drivers/net/tg3.c | |
| parent | 29ea095fb727ac48228ff2d1af484c27bf1dcbd4 (diff) | |
tg3: Preserve PCIe MPS setting for new devs
Most older tg3 devices only supported a PCIe maximum payload size of
128 bytes. More recent devices bump this limit up to 256 bytes
though. This patch modifies the code so that the MPS limit is only
enforced on those devices that only allow the 128 byte setting.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index ca3052d5c409..356b5d0f0403 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -6226,6 +6226,8 @@ static int tg3_chip_reset(struct tg3 *tp) udelay(120); if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { + u16 val16; + if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { int i; u32 cfg_val; @@ -6239,12 +6241,22 @@ static int tg3_chip_reset(struct tg3 *tp) cfg_val | (1 << 15)); } - /* Set PCIE max payload size to 128 bytes and - * clear the "no snoop" and "relaxed ordering" bits. + /* Clear the "no snoop" and "relaxed ordering" bits. */ + pci_read_config_word(tp->pdev, + tp->pcie_cap + PCI_EXP_DEVCTL, + &val16); + val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | + PCI_EXP_DEVCTL_NOSNOOP_EN); + /* + * Older PCIe devices only support the 128 byte + * MPS setting. Enforce the restriction. */ + if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) + val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; pci_write_config_word(tp->pdev, tp->pcie_cap + PCI_EXP_DEVCTL, - 0); + val16); pcie_set_readrq(tp->pdev, 4096); |