diff options
| author | Mohit Kumar <mohit.kumar@st.com> | 2014-04-14 14:22:54 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:18:43 -0600 |
| commit | 93ea33573064ccfb63d2e0c806622a14c48e87f0 (patch) | |
| tree | ac672182cd678ef382f2f9ecc03e9b4124ce52c7 /drivers/pci | |
| parent | fd1271e6a7b2adfe16eca60eb9eb7760299ad9c1 (diff) | |
PCI: designware: Fix comment for setting number of lanes
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
(cherry picked from commit 66c5c34bf80c28d370eb9bcf30153ea0304a288a)
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 6eca144752ef..a9a62ce4bf05 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; - /* set the number of lines as 4 */ + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { |