diff options
| author | Bibek Basu <bbasu@nvidia.com> | 2015-03-26 13:13:41 +0530 |
|---|---|---|
| committer | Matthew Pedro <mapedro@nvidia.com> | 2015-04-07 22:39:20 -0700 |
| commit | 62ac79266ebff845d01cf3296e54c64b49119129 (patch) | |
| tree | f536a3ab8a4f24113a8f0df5f8e1bc01ffe41bf2 /drivers/pinctrl/pinctrl-tegra124.c | |
| parent | 8b6e79f59a45c2e66975b0c27ef9d855d15208ca (diff) | |
pinctrl: tegra: Add MIPI pad control
This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.
Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.
The register is not yet documented in the TRM, here is
the description:
70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
[31:02] RESERVED
[01:01] DSIB_MODE [CSI=0,DSIB=1]
[00:00] RESERVED
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
BUG=chrome-os-partner:30799
TEST=Tested on ryu
(cherry picked from commit 489c8251776de8838547207acce199f50846ded1)
Change-Id: I424f488131e51ac793814d98d018162f0644509e
Reviewed-on: https://chromium-review.googlesource.com/219832
Reviewed-on: http://git-master/r/668725
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/723409
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra124.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-tegra124.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index 6e4ac7775055..c91640892223 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -226,6 +226,16 @@ #define TEGRA_PIN_OWR _PIN(5) #define TEGRA_PIN_CLK_32K_IN _PIN(6) #define TEGRA_PIN_JTAG_RTCK _PIN(7) +#define TEGRA_PIN_DSI_B_CLK_P _PIN(8) +#define TEGRA_PIN_DSI_B_CLK_N _PIN(9) +#define TEGRA_PIN_DSI_B_D0_P _PIN(10) +#define TEGRA_PIN_DSI_B_D0_N _PIN(11) +#define TEGRA_PIN_DSI_B_D1_P _PIN(12) +#define TEGRA_PIN_DSI_B_D1_N _PIN(13) +#define TEGRA_PIN_DSI_B_D2_P _PIN(14) +#define TEGRA_PIN_DSI_B_D2_N _PIN(15) +#define TEGRA_PIN_DSI_B_D3_P _PIN(16) +#define TEGRA_PIN_DSI_B_D3_N _PIN(17) static const struct pinctrl_pin_desc tegra124_pins[] = { PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), @@ -419,6 +429,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = { PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"), PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"), + PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"), }; static const unsigned clk_32k_out_pa0_pins[] = { @@ -1582,12 +1602,37 @@ enum tegra_mux_dt { TEGRA_MUX_DT_SYS, TEGRA_MUX_DT_CLK, TEGRA_MUX_DT_TMDS, + TEGRA_MUX_DT_CSI, + TEGRA_MUX_DT_DSI_B, }; +static const unsigned mipi_pad_ctrl_dsi_b_pins[] = { + TEGRA_PIN_DSI_B_CLK_P, + TEGRA_PIN_DSI_B_CLK_N, + TEGRA_PIN_DSI_B_D0_P, + TEGRA_PIN_DSI_B_D0_N, + TEGRA_PIN_DSI_B_D1_P, + TEGRA_PIN_DSI_B_D1_N, + TEGRA_PIN_DSI_B_D2_P, + TEGRA_PIN_DSI_B_D2_N, + TEGRA_PIN_DSI_B_D3_P, + TEGRA_PIN_DSI_B_D3_N, +}; + + static const char * const blink_groups[] = { "clk_32k_out_pa0", }; +static const char * const csi_groups[] = { + "mipi_pad_ctrl_dsi_b", +}; + +static const char * const dsi_b_groups[] = { + "mipi_pad_ctrl_dsi_b", +}; + + static const char * const cec_groups[] = { "hdmi_cec_pee3", }; @@ -2976,10 +3021,13 @@ static const struct tegra_function tegra124_functions[] = { FUNCTION(sys), FUNCTION(clk), FUNCTION(tmds), + FUNCTION(csi), + FUNCTION(dsi_b), }; #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ #define PINGROUP_REG_A 0x3000 /* bank 1 */ +#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) #define PINGROUP_REG_N(r) -1 @@ -3069,6 +3117,33 @@ static const struct tegra_function tegra124_functions[] = { .drvtype_width = 2, \ } +#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A) + +#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, f0, f1, f2, f3) \ +{ \ + .name = "mipi_pad_ctrl_" #pg_name, \ + .pins = mipi_pad_ctrl_##pg_name##_pins, \ + .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_DT_ ## f0, \ + TEGRA_MUX_DT_ ## f1, \ + TEGRA_MUX_DT_ ## f2, \ + TEGRA_MUX_DT_ ## f3, \ + }, \ + .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \ + .mux_bank = 2, \ + .mux_bit = 1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .ioreset_bit = -1, \ + .rcv_sel_bit = -1, \ + .drv_reg = -1, \ +} + + static const struct tegra_pingroup tegra124_groups[] = { /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ /* FIXME: Fill in correct data in safe column */ @@ -3306,6 +3381,8 @@ static const struct tegra_pingroup tegra124_groups[] = { DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), + /*pg_name, r, f0, f1, f2, f3 */ + MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, CSI, DSI_B, RSVD3, RSVD4) }; static int tegra124_pinctrl_suspend(u32 *pg_data) |