diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2015-08-03 12:46:38 +0300 |
|---|---|---|
| committer | Sasha Levin <alexander.levin@verizon.com> | 2016-08-16 08:25:03 -0400 |
| commit | ba42156d9552903782ab2723e5dbf3fe7275ddc7 (patch) | |
| tree | 3b0e66cf72cc29527b0bd1654b7ccc44b5096247 /drivers/pinctrl | |
| parent | e05777384e99ed3baef9459027e5318ed20f41f3 (diff) | |
pinctrl: cherryview: Serialize all register access
[ Upstream commit 4585b000ace6438d0b142746baab658056b223d9 ]
There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.
Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 732ff757a95f..eaaede70d4de 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1169,9 +1169,12 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) { struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); int pin = chv_gpio_offset_to_pin(pctrl, offset); + unsigned long flags; u32 ctrl0, cfg; + spin_lock_irqsave(&pctrl->lock, flags); ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); + spin_unlock_irqrestore(&pctrl->lock, flags); cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; @@ -1209,8 +1212,11 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); u32 ctrl0, direction; + unsigned long flags; + spin_lock_irqsave(&pctrl->lock, flags); ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); + spin_unlock_irqrestore(&pctrl->lock, flags); direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; @@ -1313,6 +1319,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) unsigned long flags; u32 intsel, value; + spin_lock_irqsave(&pctrl->lock, flags); intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); intsel &= CHV_PADCTRL0_INTSEL_MASK; intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; @@ -1323,7 +1330,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) else handler = handle_edge_irq; - spin_lock_irqsave(&pctrl->lock, flags); if (!pctrl->intr_lines[intsel]) { __irq_set_handler_locked(d->irq, handler); pctrl->intr_lines[intsel] = offset; |