pinctrl: tegra: fix drive groups configuration handling

For Tegra124, all drive groups does not supports all
configuration. The configuration which is not supported
is having the bits as -ve in their pinconfig table but
related variable is declared as unsigned making this
configuration as valid.

Correct the datatype of the drive groups configuration bits
and handling this properly across the driver to ignore the
configuration which is not supported.

Change-Id: I9b5666f7fa966df05df566196d155b516cded629
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/361999

2 files changed, 116 insertions, 65 deletions

diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index cd76cf7c68f8..46aefd9d3ec4 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -540,7 +540,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 		return -ENOTSUPP;
 	}
 
-	if (*reg < 0) {
+	if (*reg < 0 || *bit < 0) {
 		if (report_err)
 			dev_err(pmx->dev,
 				"Config param %04x not supported on group %s\n",
@@ -827,31 +827,38 @@ static void tegra_pinctrl_default_soc_init(struct tegra_pmx *pmx)
 			continue;
 		}
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].hsm_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
 				cdata->high_speed_mode);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].schmitt_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_SCHMITT,
 				cdata->schmitt);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].lpmd_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
 				cdata->low_power_mode);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].drvdn_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
 				cdata->pull_down_strength);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].drvup_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
 				cdata->pull_up_strength);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].slwf_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
 				cdata->slew_rate_falling);
 
-		tegra_pinctrl_set_config(pmx->pctl, group,
+		if (pmx->soc->groups[i].slwr_bit >= 0)
+			tegra_pinctrl_set_config(pmx->pctl, group,
 				TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
 				cdata->slew_rate_rising);
 
@@ -1001,10 +1008,10 @@ static const char *tegra_pinctrl_slew_names[TEGRA_MAX_SLEW] = {
 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
 #define LPMD(reg)       (((reg) >> 4) & 0x3)
-#define DRVDN(reg, offset)      (((reg) >> offset) & 0x1f)
-#define DRVUP(reg, offset)      (((reg) >> offset) & 0x1f)
-#define SLWR(reg, offset)       (((reg) >> offset) & 0x3)
-#define SLWF(reg, offset)       (((reg) >> offset) & 0x3)
+#define DRVDN(reg, offset, w)      (((reg) >> offset) & (BIT(w) -1))
+#define DRVUP(reg, offset, w)      (((reg) >> offset) & (BIT(w) -1))
+#define SLWR(reg, offset, w)       (((reg) >> offset) & (BIT(w) -1))
+#define SLWF(reg, offset, w)       (((reg) >> offset) & (BIT(w) -1))
 
 static const char *tegra_pinctrl_function_name(enum tegra_mux_func func)
 {
@@ -2060,6 +2067,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
 	int i;
 	int len;
 	u8 offset;
+	unsigned int width;
 
 	for (i = 0; i < pmx->soc->ngroups; i++) {
 		u32 reg;
@@ -2074,45 +2082,88 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
 
 		reg = pmx_readl(pmx, pmx->soc->groups[i].drv_bank,
 					pmx->soc->groups[i].drv_reg);
-		if (HSM_EN(reg)) {
-			seq_puts(s, "TEGRA_HSM_ENABLE");
-			len = 16;
+		if (pmx->soc->groups[i].hsm_bit >= 0) {
+			if (HSM_EN(reg)) {
+				seq_puts(s, "TEGRA_HSM_ENABLE");
+				len = 16;
+			} else {
+				seq_puts(s, "TEGRA_HSM_DISABLE");
+				len = 17;
+			}
 		} else {
-			seq_puts(s, "TEGRA_HSM_DISABLE");
-			len = 17;
+			seq_puts(s, "TEGRA_HSM_XXXXXX");
+			len = 16;
 		}
+
 		dbg_pad_field(s, 17 - len);
 
-		if (SCHMT_EN(reg)) {
-			seq_puts(s, "TEGRA_SCHMITT_ENABLE");
-			len = 21;
+		if (pmx->soc->groups[i].schmitt_bit >= 0) {
+			if (SCHMT_EN(reg)) {
+				seq_puts(s, "TEGRA_SCHMITT_ENABLE");
+				len = 21;
+			} else {
+				seq_puts(s, "TEGRA_SCHMITT_DISABLE");
+				len = 22;
+			}
 		} else {
-			seq_puts(s, "TEGRA_SCHMITT_DISABLE");
+			seq_puts(s, "TEGRA_SCHMITT_XXXXXXX");
 			len = 22;
 		}
 		dbg_pad_field(s, 22 - len);
 
-		seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
-		len = strlen(drive_name(LPMD(reg)));
+		if (pmx->soc->groups[i].lpmd_bit < 0) {
+			seq_printf(s, "TEGRA_DRIVE_XXXXX");
+			len = 5;
+		} else {
+			seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
+			len = strlen(drive_name(LPMD(reg)));
+		}
 		dbg_pad_field(s, 5 - len);
 
-		offset = pmx->soc->groups[i].drvdn_bit;
-		seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset));
-		len = DRVDN(reg, offset) < 10 ? 1 : 2;
+		if (pmx->soc->groups[i].drvdn_bit >= 0) {
+			offset = pmx->soc->groups[i].drvdn_bit;
+			width = pmx->soc->groups[i].drvdn_width;
+			seq_printf(s, "TEGRA_PULL_%lu",
+					DRVDN(reg, offset, width));
+			len = DRVDN(reg, offset, width) < 10 ? 1 : 2;
+		} else {
+			seq_printf(s, "TEGRA_PULL_XXX");
+			len = 1;
+		}
 		dbg_pad_field(s, 2 - len);
 
-		offset = pmx->soc->groups[i].drvup_bit;
-		seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset));
-		len = DRVUP(reg, offset) < 10 ? 1 : 2;
+		if (pmx->soc->groups[i].drvup_bit >= 0) {
+			offset = pmx->soc->groups[i].drvup_bit;
+			width = pmx->soc->groups[i].drvup_width;
+			seq_printf(s, "TEGRA_PULL_%lu",
+					DRVUP(reg, offset, width));
+			len = DRVUP(reg, offset, width) < 10 ? 1 : 2;
+		} else {
+			seq_printf(s, "TEGRA_PULL_XXX");
+			len = 1;
+		}
 		dbg_pad_field(s, 2 - len);
 
-		offset = pmx->soc->groups[i].slwr_bit;
-		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset)));
-		len = strlen(slew_name(SLWR(reg, offset)));
+		if (pmx->soc->groups[i].slwr_bit >= 0) {
+			offset = pmx->soc->groups[i].slwr_bit;
+			width = pmx->soc->groups[i].slwr_width;
+			seq_printf(s, "TEGRA_SLEW_%s",
+				slew_name(SLWR(reg, offset, width)));
+			len = strlen(slew_name(SLWR(reg, offset, width)));
+		} else {
+			seq_printf(s, "TEGRA_SLEW_XXXXXXX");
+			len = 7;
+		}
 		dbg_pad_field(s, 7 - len);
 
-		offset = pmx->soc->groups[i].slwf_bit;
-		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset)));
+		if (pmx->soc->groups[i].slwf_bit >= 0) {
+			offset = pmx->soc->groups[i].slwf_bit;
+			width = pmx->soc->groups[i].slwf_width;
+			seq_printf(s, "TEGRA_SLEW_%s",
+				slew_name(SLWF(reg, offset, width)));
+		} else {
+			seq_printf(s, "TEGRA_SLEW_XXXXXXX");
+		}
 
 		seq_puts(s, "},\n");
 	}
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 53eb32c58d1e..20fbb9e05862 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -99,37 +99,37 @@ struct tegra_pingroup {
 	s16 rcv_sel_reg;
 	s16 drv_reg;
 	s16 drvtype_reg;
-	u32 mux_bank:2;
-	u32 pupd_bank:2;
-	u32 tri_bank:2;
-	u32 einput_bank:2;
-	u32 odrain_bank:2;
-	u32 ioreset_bank:2;
-	u32 rcv_sel_bank:2;
-	u32 lock_bank:2;
-	u32 drv_bank:2;
-	u32 drvtype_bank:2;
-	u32 mux_bit:5;
-	u32 pupd_bit:5;
-	u32 tri_bit:5;
-	u32 einput_bit:5;
-	u32 odrain_bit:5;
-	u32 lock_bit:5;
-	u32 ioreset_bit:5;
-	u32 rcv_sel_bit:5;
-	u32 hsm_bit:5;
-	u32 schmitt_bit:5;
-	u32 lpmd_bit:5;
-	u32 drvdn_bit:5;
-	u32 drvup_bit:5;
-	u32 slwr_bit:5;
-	u32 slwf_bit:5;
-	u32 drvtype_bit:5;
-	u32 drvdn_width:6;
-	u32 drvup_width:6;
-	u32 slwr_width:6;
-	u32 slwf_width:6;
-	u32 drvtype_width:6;
+	int mux_bank;
+	int pupd_bank;
+	int tri_bank;
+	int einput_bank;
+	int odrain_bank;
+	int ioreset_bank;
+	int rcv_sel_bank;
+	int lock_bank;
+	int drv_bank;
+	int drvtype_bank;
+	int mux_bit;
+	int pupd_bit;
+	int tri_bit;
+	int einput_bit;
+	int odrain_bit;
+	int lock_bit;
+	int ioreset_bit;
+	int rcv_sel_bit;
+	int hsm_bit;
+	int schmitt_bit;
+	int lpmd_bit;
+	int drvdn_bit;
+	int drvup_bit;
+	int slwr_bit;
+	int slwf_bit;
+	int drvtype_bit;
+	int drvdn_width;
+	int drvup_width;
+	int slwr_width;
+	int slwf_width;
+	int drvtype_width;
 	const char *dev_id;
 };