diff options
author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-11-18 18:20:38 +0530 |
---|---|---|
committer | Laxman Dewangan <ldewangan@nvidia.com> | 2013-11-18 08:05:32 -0800 |
commit | 99247699329e9539cf07838ea77582eb66d8f62f (patch) | |
tree | 7cbb73b598002d15691a496c62e754aac57d127e /drivers/pinctrl | |
parent | 1e92b755ebf6ef3c667ddf75d6965d6bf4cd5833 (diff) |
pinctrl: tegra: fix the ddc_pin control register address
The DDC_SCL pin control register is placed at 0x3114.
bug 1409300
Change-Id: Ie39dea7d915845ebed5c2914d4f717d141c8195c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/332418
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/pinctrl-tegra124.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index d2bcb32c6dcb..f41255d02320 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c @@ -2909,7 +2909,7 @@ static const struct tegra_pingroup tegra124_groups[] = { PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, EXTPERIPH2, 0x3068, N, N, N), PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, DAP, 0x306c, N, N, N), PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3110, N, N, Y), - PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3124, N, N, Y), + PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3114, N, N, Y), PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3118, N, N, Y), PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N), PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N), |