diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-06-08 18:52:38 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2016-06-08 22:04:02 +0800 |
| commit | 2a61bdfdf499c3abd804458997ed7ef249e5450a (patch) | |
| tree | 7754ad5317a789447726cefdfe06db918ef19108 /drivers/rtc | |
| parent | 5f9ce4885efe4a8d51bab84a02cb1c87ca085b08 (diff) | |
MLK-12890 rtc: snvs: update time read function
When CPU/AXI/AHB are running at 24MHz, IPG at
12MHz, two consecutive reads of RTC timer registers
never get same value, so we need to skip the low
15 bits, only make sure the second value are same
during two consecutive reads.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'drivers/rtc')
| -rw-r--r-- | drivers/rtc/rtc-snvs.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c index 950c5d0b6dca..b33be8f5cb13 100644 --- a/drivers/rtc/rtc-snvs.c +++ b/drivers/rtc/rtc-snvs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -64,7 +64,12 @@ static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) read2 <<= 32; regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); read2 |= val; - } while (read1 != read2); + /* + * when CPU/BUS are running at low speed, there is chance that + * we never get same value during two consecutive read, so here + * we only compare the second value. + */ + } while ((read1 >> CNTR_TO_SECS_SH) != (read2 >> CNTR_TO_SECS_SH)); /* Convert 47-bit counter to 32-bit raw second count */ return (u32) (read1 >> CNTR_TO_SECS_SH); |