diff options
| author | Gao Pan <pandy.gao@nxp.com> | 2018-03-06 09:25:10 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | c5599ce52b52b2c8bd994f36a45bff0bea3fddb9 (patch) | |
| tree | dd76d6787827d136dc195845e9d4fe0768ab0122 /drivers/spi | |
| parent | 6330040d8bd6d4fa7a1b573448967b2f893a2be2 (diff) | |
MLK-17672 lpspi: fix clock polarity issue and DBT issue
1. Fix code error of changing lpspi clock polarity.
2. Set one SPI clock period for DBT parameter.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Reviewed-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-fsl-lpspi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index 0872607280bf..6f2566ecac25 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -197,7 +197,7 @@ static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi) temp |= TCR_CONT; temp |= fsl_lpspi->config.bpw - 1; temp |= fsl_lpspi->config.prescale << 27; - temp |= (fsl_lpspi->config.mode & 0x11) << 30; + temp |= (fsl_lpspi->config.mode & 0x3) << 30; temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; writel(temp, fsl_lpspi->base + IMX7ULP_TCR); @@ -243,7 +243,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) if (prescale == 8 && scldiv >= 256) return -EINVAL; - writel(scldiv, fsl_lpspi->base + IMX7ULP_CCR); + writel(scldiv | (scldiv << 8), fsl_lpspi->base + IMX7ULP_CCR); dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n", perclk_rate, config.speed_hz, prescale, scldiv); |