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authorLaxman Dewangan <ldewangan@nvidia.com>2012-05-14 13:58:02 +0530
committerSimone Willett <swillett@nvidia.com>2012-05-18 13:45:03 -0700
commita763d40775269f8e29fea5780000014178eaf4b3 (patch)
tree791f79739809c31012a7ec41c94eefd7ea9d1eaf /drivers/spi
parent3fa0179bff425820a1c7aed0e55fac4f18f99658 (diff)
spi: tegra: register interrupt as ONESHOT
The Tegra spi's engine is design as it generates interrupt when any error occurs and it keep transferring data. It does not stop the engine once error occurred and interrupt generated. This may cause reentry of ISR as on error case, isr get called where it clears interrupt and because it is still in progress, it again interrupts and schedule the thread. The second time scheduling of the isr/thread can cause the issue in queue management and sw state. So Making the interrupt as ONESHOT so that the interrupt will not get schedule until the engine is reset in error case. Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/101547 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com> Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-tegra.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index 3f913389dd7c..cfc610102c11 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -1265,7 +1265,7 @@ static int __init spi_tegra_probe(struct platform_device *pdev)
sprintf(tspi->port_name, "tegra_spi_%d", pdev->id);
ret = request_threaded_irq(tspi->irq, spi_tegra_isr,
- spi_tegra_isr_thread, IRQF_DISABLED,
+ spi_tegra_isr_thread, IRQF_ONESHOT,
tspi->port_name, tspi);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",