MLK-9986-5 spi: spi-imx: decrease tx fifo wartermark level

We set both wartermark of txfifo and rxfifo 32 as half of fifo length 64.
That will cause easy rxfifo overflow:
If there is 31 bytes in rxfifo, rx script will wait the next dma request
(the 32th data come into the rxfifo) and schedule out to tx script. Once
tx script start to run, the rx script need to wait tx script finish even
if its priority higher than tx. Meanwhile, spi slave device may input
data continous, plus the rx data which triggered by new tx script(32 bytes).
That will quickly consume whole 64 bytes fifo, so we keep 16bytes availbale
even in the worst case new tx script triggered during two rx transfer. That
may slow down tx slightly, but better than overflow and RX DMA timeout.

Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 16043ad0ad96aa04a90614e473aa17980af4b8af)
(cherry picked from commit 819efee83b7b1f47685dca6fad6bbe17f1c42092)
(cherry picked from commit 5c4c7d05bbba0ea2b26ef2f3ae83119d5eada235)

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index a6e34f05d44d..7d7085cb7148 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -839,7 +839,7 @@ static int spi_imx_dma_configure(struct spi_master *master,
 	tx.direction = DMA_MEM_TO_DEV;
 	tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
 	tx.dst_addr_width = buswidth;
-	tx.dst_maxburst = spi_imx->wml;
+	tx.dst_maxburst = spi_imx->wml / 2;
 	ret = dmaengine_slave_config(master->dma_tx, &tx);
 	if (ret) {
 		dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);