diff options
| author | Geert Uytterhoeven <geert+renesas@linux-m68k.org> | 2014-01-12 11:27:38 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-01-13 12:10:01 +0000 |
| commit | fbe5072bbeac5362edc8c49435b76e6df75a9d95 (patch) | |
| tree | 23deadb58e97ab820553012855554515571adf8a /drivers/spi | |
| parent | 6ab4865b7e34e707857107ca76c0b98d87a992dd (diff) | |
spi: rspi: Add more QSPI register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-rspi.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 1f69343689f9..4a2c7592b5eb 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -62,12 +62,12 @@ #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ /*qspi only */ -#define QSPI_SPBFCR 0x18 -#define QSPI_SPBDCR 0x1a -#define QSPI_SPBMUL0 0x1c -#define QSPI_SPBMUL1 0x20 -#define QSPI_SPBMUL2 0x24 -#define QSPI_SPBMUL3 0x28 +#define QSPI_SPBFCR 0x18 /* Buffer Control Register */ +#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ +#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ +#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ +#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ +#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ /* SPCR - Control Register */ #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ @@ -79,6 +79,9 @@ /* RSPI on SH only */ #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ +/* QSPI on R-Car M2 only */ +#define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ +#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ /* SSLP - Slave Select Polarity Register */ #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ @@ -91,6 +94,9 @@ #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ +#define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ +#define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ + /* SPSR - Status Register */ #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ #define SPSR_TEND 0x40 /* Transmit End */ @@ -151,6 +157,13 @@ #define SPCMD_SPB_24BIT 0x0100 #define SPCMD_SPB_32BIT 0x0200 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ +#define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ +#define SPCMD_SPIMOD1 0x0040 +#define SPCMD_SPIMOD0 0x0020 +#define SPCMD_SPIMOD_SINGLE 0 +#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 +#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 +#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ |