diff options
| author | Ian Abbott <abbotti@mev.co.uk> | 2016-05-20 14:49:12 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-06-17 20:59:52 -0700 |
| commit | ed5df5db92b3148a94bfa9b025a8e21c6a9518e6 (patch) | |
| tree | e3ebdb9bd09b0a066238c18179112ff8be707b55 /drivers/staging/comedi/drivers/plx9080.h | |
| parent | e0045472e0d9a398d68b8570b748a49a091b12fa (diff) | |
staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA register values
Replace the existing macros in "plx9080.h" that define values for the
DMCFGA register. Use the prefix `PLX_DMCFGA_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/comedi/drivers/plx9080.h')
| -rw-r--r-- | drivers/staging/comedi/drivers/plx9080.h | 29 |
1 files changed, 22 insertions, 7 deletions
diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index ab9083791105..e544327fe60f 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -266,13 +266,28 @@ struct plx_dma_desc { /* PCI Configuration Address Register for Direct Master to PCI IO/CFG */ #define PLX_REG_DMCFGA 0x002c -#define CAR_CT0 0x00000000 /* Config Type 0 */ -#define CAR_CT1 0x00000001 /* Config Type 1 */ -#define CAR_REG 0x000000FC /* Register Number Bits */ -#define CAR_FUN 0x00000700 /* Function Number Bits */ -#define CAR_DEV 0x0000F800 /* Device Number Bits */ -#define CAR_BUS 0x00FF0000 /* Bus Number Bits */ -#define CAR_CFG 0x80000000 /* Config Spc Access Enable */ +/* Congiguration Type */ +#define PLX_DMCFGA_TYPE0 (BIT(0) * 0) +#define PLX_DMCFGA_TYPE1 (BIT(0) * 1) +#define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0) +/* Register Number */ +#define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f)) +#define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2) +#define PLX_DMCFGA_REGNUM_SHIFT 2 +/* Function Number */ +#define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7)) +#define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8) +#define PLX_DMCFGA_FUNCNUM_SHIFT 8 +/* Device Number */ +#define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f)) +#define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11) +#define PLX_DMCFGA_DEVNUM_SHIFT 11 +/* Bus Number */ +#define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff)) +#define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16) +#define PLX_DMCFGA_BUSNUM_SHIFT 16 +/* Configuration Enable */ +#define PLX_DMCFGA_CONFIGEN BIT(31) /* * Mailbox Register N (N <= 7) |