diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2015-06-29 15:00:59 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2015-08-04 17:51:28 +0200 |
| commit | 1f838086495d233570efa6c3e8601eeafdfa9989 (patch) | |
| tree | 7d999f375a0f5e68b935f145363652856724f34c /drivers/tty/serial/fsl_lpuart.c | |
| parent | fc60861b91c6585740e9a502fa4008b2f4694b22 (diff) | |
tty: serial: fsl_lpuart: fix clearing of receive flag
Commit 8e4934c6d6c6 ("tty: serial: fsl_lpuart: clear receive flag
on FIFO flush") implemented clearing of the receive flag by reading
the status register only. It turned out that even though we flush
the FIFO afterwards, a explicit read of the data register is still
required.
This leads to a FIFO underrun. To avoid this, follow the advice in
the overrun "Operation section": Unconditionally clear RXUF after
using RXFLUSH.
Diffstat (limited to 'drivers/tty/serial/fsl_lpuart.c')
| -rw-r--r-- | drivers/tty/serial/fsl_lpuart.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 25f395bf3d46..921f68a85b5c 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -925,13 +925,16 @@ static void lpuart_setup_watermark(struct lpuart_port *sport) writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, sport->port.membase + UARTPFIFO); - /* explicitly clear RDRF */ - readb(sport->port.membase + UARTSR1); - /* flush Tx and Rx FIFO */ writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); + /* explicitly clear RDRF */ + if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { + readb(sport->port.membase + UARTDR); + writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); + } + writeb(0, sport->port.membase + UARTTWFIFO); writeb(1, sport->port.membase + UARTRWFIFO); |