diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-01-22 15:33:21 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-12-24 01:27:27 +0100 |
| commit | b57d69fc085677248f2e1d404f005f9d04a8595c (patch) | |
| tree | bab68bbd7bbab1985a01ef517629004b19d17983 /drivers/tty/serial | |
| parent | 3514607c6e658a94d6d298ae54480e5d7c4c323a (diff) | |
tty: serial: imx: disable DCD and RI interrupts
If the UART is in DTE mode, the signals DCD and RI are inputs. In
this case, the control bits in UCR3_DCD and UCR3_RI control the
interrupt of those two inputs. The two bits are 1 on reset, hence
leading to an interrupt if one of those signal changes... However,
as of now the interrupt handler does not handle these interrupts,
leading to a interrupt strom.
Solve the issue by explicitly disabling the two interrupts during
initialization.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 2d027fec8264daa4cda1bcc81cabb91bd97cde0b)
(cherry picked from commit 0d85191ac6663ea3e2ff84d96f20c62144549f27)
Diffstat (limited to 'drivers/tty/serial')
| -rw-r--r-- | drivers/tty/serial/imx.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 5f7452eaa728..3c5fdab7fac7 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1281,6 +1281,13 @@ static int imx_startup(struct uart_port *port) writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); + /* Disable DCDDELT/RIDELT interrupts */ + if (!is_imx1_uart(sport) && sport->dte_mode) { + temp = readl(sport->port.membase + UCR3); + temp &= ~(UCR3_DCD | UCR3_RI); + writel(temp, sport->port.membase + UCR3); + } + /* Reset fifo's and state machines */ i = 100; |