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authorJay Cheng <jacheng@nvidia.com>2012-04-04 20:30:58 -0400
committerVarun Colbert <vcolbert@nvidia.com>2012-05-18 16:07:48 -0700
commit2fbd01fd8fd8954e6ec4ee22b3a2ab0506f76818 (patch)
tree6416481b49b5bb4828a1d5af097239db9f96044f /drivers/video/tegra/dc/dc.c
parent1508ff0adf5096ae3d601f8c02df7609814e0c7c (diff)
video: tegra: dc: recover underflow error
1. set UF_LINE_FLUSH to 0 by default. 2. if it gets 4 consecutive frames with underflows, enable UF_LINE_FLUSH to get rid of underflow condition. Signed-off-by: Jay Cheng <jacheng@nvidia.com> Change-Id: I6d647d958484ee355809036bec7ca1b0c716017b Reviewed-on: http://git-master/r/103227 Reviewed-by: Michael I Gold <gold@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dc.c')
-rw-r--r--drivers/video/tegra/dc/dc.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 51af1e0..5203fbb 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -2155,6 +2155,26 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc)
dc->windows[i].underflows = 0;
}
#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ if (dc->windows[i].underflows > 4) {
+ printk("%s:dc in underflow state."
+ " enable UF_LINE_FLUSH to clear up\n",
+ __func__);
+ tegra_dc_writel(dc, UF_LINE_FLUSH,
+ DC_DISP_DISP_MISC_CONTROL);
+ tegra_dc_writel(dc, GENERAL_UPDATE,
+ DC_CMD_STATE_CONTROL);
+ tegra_dc_writel(dc, GENERAL_ACT_REQ,
+ DC_CMD_STATE_CONTROL);
+
+ tegra_dc_writel(dc, 0,
+ DC_DISP_DISP_MISC_CONTROL);
+ tegra_dc_writel(dc, GENERAL_UPDATE,
+ DC_CMD_STATE_CONTROL);
+ tegra_dc_writel(dc, GENERAL_ACT_REQ,
+ DC_CMD_STATE_CONTROL);
+ }
+#endif
} else {
dc->windows[i].underflows = 0;
}
@@ -2476,7 +2496,9 @@ static int tegra_dc_init(struct tegra_dc *dc)
tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
-
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
+#endif
/* enable interrupts for vblank, frame_end and underflows */
tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
DC_CMD_INT_ENABLE);