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authorMin-wuk Lee <mlee@nvidia.com>2011-11-14 13:48:18 +0900
committerVarun Wadekar <vwadekar@nvidia.com>2011-12-21 12:06:26 +0530
commitdb128e88fee3435c10ba0b9a2c1479b85a14ede7 (patch)
treece830a6c2b59681ddb75ab4d4c2112c87a82b640 /drivers/video/tegra/dc/dc.c
parent6f73e3dafe7ab1729978dc2149aadd7ad74d8686 (diff)
video: tegra: dc: direct dc out pins polarity setting
dc vsync, hsync, DE and pclk polarity in kernel can be different with bootloader setting for a short time when default polarity value is written. This can generate momentary panel flicker in kernel boot. Set the first polarity based on board dc out pin polarity information directly if needed. Bug 891444 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/59895 (cherry picked from commit 8e5bfd5702067309171b62a6be5471bfab68a31e) Change-Id: I80c703792ea5a9596d4cf42ef19115cbf4d556f6 Reviewed-on: http://git-master/r/69711 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dc.c')
-rw-r--r--drivers/video/tegra/dc/dc.c29
1 files changed, 6 insertions, 23 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 81e88bd..04de0ed 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -54,6 +54,9 @@
#define TEGRA_CRC_LATCHED_DELAY 34
+#define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL 0x01000000
+#define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL 0x0
+
#ifndef CONFIG_TEGRA_FPGA_PLATFORM
#define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
#else
@@ -1611,18 +1614,6 @@ static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode
tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
DC_DISP_DATA_ENABLE_OPTIONS);
- val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
- if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
- val |= PIN1_LVS_OUTPUT;
- else
- val &= ~PIN1_LVS_OUTPUT;
-
- if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
- val |= PIN1_LHS_OUTPUT;
- else
- val &= ~PIN1_LHS_OUTPUT;
- tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
-
/* TODO: MIPI/CRT/HDMI clock cals */
val = DISP_DATA_FORMAT_DF1P1C;
@@ -1790,7 +1781,7 @@ tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
}
EXPORT_SYMBOL(tegra_dc_config_pwm);
-static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
+void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
const struct tegra_dc_out_pin *pins,
const unsigned int n_pins)
{
@@ -1843,8 +1834,8 @@ static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
}
}
- pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
- pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
+ pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
+ pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
pol1 |= set1;
pol1 &= ~unset1;
@@ -2363,10 +2354,6 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
- if (dc->out->out_pins)
- tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
- dc->out->n_out_pins);
-
if (dc->out->postpoweron)
dc->out->postpoweron();
@@ -2419,10 +2406,6 @@ static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
- if (dc->out->out_pins)
- tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
- dc->out->n_out_pins);
-
if (dc->out->postpoweron)
dc->out->postpoweron();