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authorKen Chang <kenc@nvidia.com>2012-05-15 18:02:04 +0800
committerSimone Willett <swillett@nvidia.com>2012-06-25 17:34:40 -0700
commit81a8d469a7e9d70d0a2cc0345ddf509038bb620a (patch)
tree209eb35319974f4b8b72183b12fdbc45304a9040 /drivers/video/tegra/dc/dc_priv.h
parentcd17fa91e37f8b867ab1ae2759bda03e950fdf83 (diff)
arm: tegra: kai: Fix panel power on/off sequence
Panel power on/off sequence should meet the panel spec as below. power on: 1. EN_VDD_PNL 2. PCLK 3. LVDS_EN 4. LCD_BL_PWN power off: 1. LCD_BL_PWN 2. LVDS_EN 3. PCLK 4. EN_VDD_PNL Pixel clock on/off is controlled by dc driver, we need to separate the setting of panel enable/disable into two parts. The first, i.e., before pclk on/off, is done in kai_panel_enable()/kai_panel_prepoweroff(). And the second part, i.e., after pclk on/off, is done in kai_panel_postpoweron()/kai_panel_disable(). bug 976081 Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: http://git-master/r/102555 Reviewed-by: Artiste Hsu <chhsu@nvidia.com> Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> (cherry picked from commit 8149532e20729c359eb1680297f19a8f46343054) Change-Id: Ifc0d60c2caabf60f4186179e64756a4caabf9af6 Reviewed-on: http://git-master/r/110297 Tested-by: Ken Chang <kenc@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Artiste Hsu <chhsu@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dc_priv.h')
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