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authorXin Xie <xxie@nvidia.com>2011-06-03 20:47:14 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:47:11 -0800
commitd21b89daf5e816d00855133f5e31cd40ce104d9b (patch)
treef0d6b5ce3ced33c0c7641016bf6edc4142b50ffc /drivers/video/tegra/dc/dc_priv.h
parentaf504e4dbb71172136b2db26b2911da57bffc72e (diff)
tegra: dc: set EMC clock dynamically
If the screen is idle (no POST for some time), reduce the DC EMC clock according the windows size. If external display connected, the EMC clock will not be reduced. BUG 828306 Original-Change-Id: I6fb62ce6baf3380737c76b71f16e38ad6465a667 Reviewed-on: http://git-master/r/37106 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re2b2c8b1a57c2a04b61c338b0b50e41d8c11ad65
Diffstat (limited to 'drivers/video/tegra/dc/dc_priv.h')
-rw-r--r--drivers/video/tegra/dc/dc_priv.h39
1 files changed, 37 insertions, 2 deletions
diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h
index f6b560b98801..77ed9afe2661 100644
--- a/drivers/video/tegra/dc/dc_priv.h
+++ b/drivers/video/tegra/dc/dc_priv.h
@@ -26,6 +26,34 @@
#include "../host/dev.h"
+#define WIN_IS_TILED(win) ((win)->flags & TEGRA_WIN_FLAG_TILED)
+#define WIN_IS_ENABLED(win) ((win)->flags & TEGRA_WIN_FLAG_ENABLED)
+#define WIN_USE_V_FILTER(win) ((win)->h != (win)->out_h)
+#define WIN_USE_H_FILTER(win) ((win)->w != (win)->out_w)
+
+#define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
+
+/* DDR: 8 bytes transfer per clock */
+#define DDR_BW_TO_FREQ(bw) ((bw) / 8)
+
+#if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
+#else
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
+#endif
+
+/*
+ * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is
+ * discarded in tiling mode.
+ */
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define TILED_WINDOWS_BW_MULTIPLIER 1
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#define TILED_WINDOWS_BW_MULTIPLIER 2
+#else
+#warning "need to revisit memory tiling effects on DC"
+#endif
+
struct tegra_dc;
struct tegra_dc_blend {
@@ -52,8 +80,6 @@ struct tegra_dc_out_ops {
};
struct tegra_dc {
- struct list_head list;
-
struct nvhost_device *ndev;
struct tegra_dc_platform_data *pdata;
@@ -63,6 +89,8 @@ struct tegra_dc {
struct clk *clk;
struct clk *emc_clk;
+ int emc_clk_rate;
+ int new_emc_clk_rate;
bool enabled;
bool suspended;
@@ -92,6 +120,7 @@ struct tegra_dc {
unsigned long underflow_mask;
struct work_struct reset_work;
+ struct delayed_work reduce_emc_clk_work;
struct completion vblank_complete;
@@ -155,6 +184,12 @@ static inline void *tegra_dc_get_outdata(struct tegra_dc *dc)
return dc->out_data;
}
+static inline unsigned long tegra_dc_get_default_emc_clk_rate(
+ struct tegra_dc *dc)
+{
+ return dc->pdata->emc_clk_rate ? dc->pdata->emc_clk_rate : ULONG_MAX;
+}
+
void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk);
extern struct tegra_dc_out_ops tegra_dc_rgb_ops;