diff options
| author | Laurence Harrison <lharrison@nvidia.com> | 2011-03-15 21:43:45 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:44:59 -0800 |
| commit | f8756378e4ceaceccfc4cedf39d9c879380ee436 (patch) | |
| tree | 51a939d15267b199383c5902dbf481314de3dbd0 /drivers/video/tegra/dc/dc_reg.h | |
| parent | 0207f39caeabda56e3de6e3949c17faa01b2e20d (diff) | |
video: tegra: Added initial smartdimmer support
includes:
1.) changes to DC init to add SD functionality
2.) changes to DC flip to add SD functionality
Original-Change-Id: I8c729e16e2b8a5a4158697b99cc4b3d07bf02001
Reviewed-on: http://git-master/r/21452
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I4ad3ee3778a0e859e0d2b0c36ee6369193795cd3
Rebase-Id: Rd133da1af5c8b283b1886b025b8b1880ec61fde0
Diffstat (limited to 'drivers/video/tegra/dc/dc_reg.h')
| -rw-r--r-- | drivers/video/tegra/dc/dc_reg.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dc_reg.h b/drivers/video/tegra/dc/dc_reg.h index 11bce9a4e3ea..c7f4a30223dc 100644 --- a/drivers/video/tegra/dc/dc_reg.h +++ b/drivers/video/tegra/dc/dc_reg.h @@ -450,4 +450,69 @@ #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 #define DC_WINBUF_UFLOW_STATUS 0x80a + +#define DC_DISP_SD_CONTROL 0x4c2 +#define SD_ENABLE_NORMAL (1 << 0) +#define SD_ENABLE_ONESHOT (2 << 0) +#define SD_USE_VID_LUMA (1 << 2) +#define SD_BIN_WIDTH_ONE (0 << 3) +#define SD_BIN_WIDTH_TWO (1 << 3) +#define SD_BIN_WIDTH_FOUR (2 << 3) +#define SD_BIN_WIDTH_EIGHT (3 << 3) +#define SD_AGGRESSIVENESS(x) (((x) & 0x7) << 5) +#define SD_HW_UPDATE_DLY(x) (((x) & 0x3) << 8) +#define SD_ONESHOT_ENABLE (1 << 10) +#define SD_CORRECTION_MODE_AUTO (0 << 11) +#define SD_CORRECTION_MODE_MAN (1 << 11) + +#define DC_DISP_SD_CSC_COEFF 0x4c3 +#define SD_CSC_COEFF_R(x) (((x) & 0xf) << 4) +#define SD_CSC_COEFF_G(x) (((x) & 0xf) << 12) +#define SD_CSC_COEFF_B(x) (((x) & 0xf) << 20) + +#define DC_DISP_SD_LUT(i) (0x4c4 + i) +#define DC_DISP_SD_LUT_NUM 9 +#define SD_LUT_R(x) (((x) & 0xff) << 0) +#define SD_LUT_G(x) (((x) & 0xff) << 8) +#define SD_LUT_B(x) (((x) & 0xff) << 16) + +#define DC_DISP_SD_FLICKER_CONTROL 0x4cd +#define SD_FC_TIME_LIMIT(x) (((x) & 0xff) << 0) +#define SD_FC_THRESHOLD(x) (((x) & 0xff) << 8) + +#define DC_DISP_SD_PIXEL_COUNT 0x4ce + +#define DC_DISP_SD_HISTOGRAM(i) (0x4cf + i) +#define DC_DISP_SD_HISTOGRAM_NUM 8 +#define SD_HISTOGRAM_BIN_0(val) (((val) & (0xff << 0)) >> 0) +#define SD_HISTOGRAM_BIN_1(val) (((val) & (0xff << 8)) >> 8) +#define SD_HISTOGRAM_BIN_2(val) (((val) & (0xff << 16)) >> 16) +#define SD_HISTOGRAM_BIN_3(val) (((val) & (0xff << 24)) >> 24) + +#define DC_DISP_SD_BL_PARAMETERS 0x4d7 +#define SD_BLP_TIME_CONSTANT(x) (((x) & 0x7ff) << 0) +#define SD_BLP_STEP(x) (((x) & 0xff) << 8) + +#define DC_DISP_SD_BL_TF(i) (0x4d8 + i) +#define DC_DISP_SD_BL_TF_NUM 4 +#define SD_BL_TF_POINT_0(x) (((x) & 0xff) << 0) +#define SD_BL_TF_POINT_1(x) (((x) & 0xff) << 8) +#define SD_BL_TF_POINT_2(x) (((x) & 0xff) << 16) +#define SD_BL_TF_POINT_3(x) (((x) & 0xff) << 24) + +#define DC_DISP_SD_BL_CONTROL 0x4dc +#define SD_BLC_MODE_MAN (0 << 0) +#define SD_BLC_MODE_AUTO (1 << 1) +#define SD_BLC_BRIGHTNESS(val) (((val) & (0xff << 8)) >> 8) + +#define DC_DISP_SD_HW_K_VALUES 0x4dd +#define SD_HW_K_R(val) (((val) & (0x3ff << 0)) >> 0) +#define SD_HW_K_G(val) (((val) & (0x3ff << 10)) >> 10) +#define SD_HW_K_B(val) (((val) & (0x3ff << 20)) >> 20) + +#define DC_DISP_SD_MAN_K_VALUES 0x4de +#define SD_MAN_K_R(x) (((x) & 0x3ff) << 0) +#define SD_MAN_K_G(x) (((x) & 0x3ff) << 10) +#define SD_MAN_K_B(x) (((x) & 0x3ff) << 20) + #endif |