diff options
| author | Animesh Kishore <ankishore@nvidia.com> | 2012-01-03 14:30:41 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-06 17:08:47 +0530 |
| commit | b26b30bbe9359e48a722198938e4299b17f7cc5c (patch) | |
| tree | db785528f766f8d80b755f12f75791109f828233 /drivers/video/tegra/dc/dsi.c | |
| parent | fde0dd459ac5048614a4f4bf4cf86224480c846d (diff) | |
video: tegra: dsi: Fix mipi continuous clk disable
Fix for stopping mipi high speed continuous clk.
Bug 903878
Change-Id: Id318fabd9c6aef116a60608c6f444846172f4803
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/72968
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
| -rw-r--r-- | drivers/video/tegra/dc/dsi.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index 5ee7671a79fa..506dfd7437af 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -1008,18 +1008,19 @@ static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc, if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); - val = tegra_dsi_readl(dsi, DSI_CONTROL); - val &= ~DSI_CONTROL_HS_CLK_CTRL(1); - val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY); - tegra_dsi_writel(dsi, val, DSI_CONTROL); - - /* TODO: issue a cmd */ + tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL); + /* stabilization delay */ + udelay(300); val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL); val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1); val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW); tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL); + tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL); + /* stabilization delay */ + udelay(300); + dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT; dsi->status.clk_out = DSI_PHYCLK_OUT_DIS; } |