diff options
| author | Kevin Huang <kevinh@nvidia.com> | 2012-02-03 18:02:42 -0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-02-15 01:08:18 -0800 |
| commit | 24ee99196e2b8a56f12b867b4e1e6e6c54b36e76 (patch) | |
| tree | 2714eaeb3d0c35fc7bd02a0ce5944e712c30995a /drivers/video/tegra/dc/dsi.c | |
| parent | 48c516dc71c28bb1eae8e5e451e22c467cc139b1 (diff) | |
video: tegra: dc: Schedule delayed work to clear emc bandwidth.
Bug 932840
Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/83645
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
| -rw-r--r-- | drivers/video/tegra/dc/dsi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index b3dd079d449e..544703dc8a48 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -954,6 +954,12 @@ static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc, /* Set up pixel clock */ dc->shift_clk_div = dsi->shift_clk_div; dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div; + /* TODO: Define one shot work delay in board file. */ + /* Since for one-shot mode, refresh rate is usually set larger than + * expected refresh rate, it needs at least 3 frame period. Less + * delay one shot work is, more powering saving we have. */ + dc->one_shot_delay_ms = 4 * + DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate); /* Enable DSI clock */ tegra_dc_setup_clk(dc, dsi->dsi_clk); |