V3L: T124: dc: Support 1920x1200 mode

To support 1920x1200 HDMI monitor for T124.

- To reserve enough space for frame buffers for screen resolution up to
  1920x1200.  Each pixel consists with 4 bytes and a display controller
  needs two set of FB, so each DC needs FB space reserved for
    1920 * 1200 * 4 * 2 = 18432000 = 18M bytes
  And the T124 has two DC.
- To limit the parent of HDMI pclk to 600MHz.  Usually the pll_d2 is the
  parent clock of hdmi pclk and T124 has 600MHz limit on it.
  This change needs to be reviewed in the bug 1420652 because setting
  the hdmi pclk has some problem with certain value.

Bug 1413335

Change-Id: If7f86e6747d3e38c630b69d84ddb20e88329ef9e
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/334876
(cherry picked from commit 4ff582c659949d66265f4b37722bcbc7f151996a)
Reviewed-on: http://git-master/r/359120
Reviewed-by: Sungwook Kim <sungwookk@nvidia.com>
Tested-by: Sungwook Kim <sungwookk@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
index 2159ff6a67a8..7f03027a9555 100644
--- a/drivers/video/tegra/dc/hdmi.c
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -2010,6 +2010,11 @@ static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
 		rate = dc->mode.pclk * 2;
 		while (rate < 400000000)
 			rate *= 2;
+		/* If the rate exceeds the max controller clock, stick with
+		 * rate * 2. Is there a better way to query max clock,
+		 * clk_get_max_rate() is confined to arch/arm/mach-tegra */
+		if (rate > 600000000)
+			rate /= 2;
 	}
 #else
 	rate = dc->mode.pclk * 2;