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authorRobert Morell <rmorell@nvidia.com>2011-07-15 18:47:06 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:48:44 -0800
commit9d83aa30476a649cc2f0cab5bbf1ffd7e4384bb2 (patch)
tree80cf7af9bb75f7c5b4bb374ee41981b3d84d1bfe /drivers/video/tegra/fb.c
parentec95801e405b5f812c9d1e5ed49adf083721bae3 (diff)
video: tegra: dc: Separate allocations for U and V
Currently, dc_ext only takes a single nvmap memory ID per overlay, even in the YUV case (the U and V planes are expected to be differentiated using an offset from the beginning of the nvmap allocation). This is problematic for some software flows, such as certain video interlacing algorithms that will vary the luma plane while keeping the chrome plane constant. This change allows dc_ext clients to specify a different nvmap allocation for each of the Y, U, and V planes. If a YUV surface is used and no U or V plane allocation is specified, the old behavior is preserved: the U and V offsets are assumed to be within the same allocation as Y. Note: this changes the behavior of the offset parameter: the old code added offset to offset_u and offset_v when using it. The new code treats all three offsets as relative to the beginning of the allocation. It also fixes a bug in the code where offset was applied twice to the Y plane. I believe this is safe because the presence of this bug means that no existing clients are using offset != 0 (or if they are, they're already broken). Signed-off-by: Robert Morell <rmorell@nvidia.com> Bug 850882 Original-Change-Id: I230e03db25baaae73a3bdc0d45a2aec162b87fa4 Reviewed-on: http://git-master/r/41471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra6dd17a50de7150edf104d2a6c9b3b9949919022
Diffstat (limited to 'drivers/video/tegra/fb.c')
-rw-r--r--drivers/video/tegra/fb.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/tegra/fb.c b/drivers/video/tegra/fb.c
index b7acecc8f562..b170bcdcba2c 100644
--- a/drivers/video/tegra/fb.c
+++ b/drivers/video/tegra/fb.c
@@ -111,8 +111,8 @@ static int tegra_fb_set_par(struct fb_info *info)
tegra_fb->win->stride = round_up(info->fix.line_length,
TEGRA_LINEAR_PITCH_ALIGNMENT);
tegra_fb->win->stride_uv = 0;
- tegra_fb->win->offset_u = 0;
- tegra_fb->win->offset_v = 0;
+ tegra_fb->win->phys_addr_u = 0;
+ tegra_fb->win->phys_addr_v = 0;
}
if (var->pixclock) {
@@ -436,8 +436,8 @@ struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
win->z = 0;
win->phys_addr = fb_phys;
win->virt_addr = fb_base;
- win->offset_u = 0;
- win->offset_v = 0;
+ win->phys_addr_u = 0;
+ win->phys_addr_v = 0;
win->stride = fb_data->xres * fb_data->bits_per_pixel / 8;
/* Pad the stride to 16-byte boundary. */
win->stride = round_up(win->stride, TEGRA_LINEAR_PITCH_ALIGNMENT);