diff options
| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2012-11-06 15:48:51 +0200 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:27:36 -0700 |
| commit | fc50f7e531ad432cf6d326834857dd5e47e75970 (patch) | |
| tree | 0bb516ab54891df55810793210e01306810efe86 /drivers/video/tegra/host/t114/t114.c | |
| parent | 263fe124e7fcf34ba9ce6d69771a1bd4e22c58dd (diff) | |
video: tegra: host: Fix CDMA timeout reset for 2D
When we have channel timeout, reset even modules for which we do not
have power gate id. As 2D needs channel teardown after reset, add
that to the reset sequence.
Add teardown fields to Tegra3 hardware headers. As we regenerate
hardware headers, Tegra11 boilerplate is changed a bit, too.
Change-Id: Ib3fd5744a9fa4faef0c6c8b83b6826732771a29f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/161642
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/host/t114/t114.c')
| -rw-r--r-- | drivers/video/tegra/host/t114/t114.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/video/tegra/host/t114/t114.c b/drivers/video/tegra/host/t114/t114.c index e5d0a9d3e564..26cbdaeae2a8 100644 --- a/drivers/video/tegra/host/t114/t114.c +++ b/drivers/video/tegra/host/t114/t114.c @@ -120,7 +120,8 @@ static struct nvhost_device_data tegra_gr3d03_info = { .waitbases = BIT(NVWAITBASE_3D), .modulemutexes = BIT(NVMODMUTEX_3D), .class = NV_GRAPHICS_3D_CLASS_ID, - .clocks = { {"gr3d", UINT_MAX, 8}, {"emc", UINT_MAX, 75} }, + .clocks = { {"gr3d", UINT_MAX, 8, true}, + {"emc", UINT_MAX, 75} }, .powergate_ids = { TEGRA_POWERGATE_3D, -1 }, NVHOST_DEFAULT_CLOCKGATE_DELAY, .can_powergate = true, @@ -143,7 +144,7 @@ static struct nvhost_device_data tegra_gr2d03_info = { .waitbases = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1), .modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) | BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B), - .clocks = { {"gr2d", 0, 7}, {"epp", 0, 10}, + .clocks = { {"gr2d", 0, 7, true}, {"epp", 0, 10, true}, {"emc", 300000000, 75 } }, .powergate_ids = { TEGRA_POWERGATE_HEG, -1 }, .clockgate_delay = 0, @@ -238,7 +239,8 @@ static struct nvhost_device_data tegra_msenc02_info = { .syncpts = BIT(NVSYNCPT_MSENC), .waitbases = BIT(NVWAITBASE_MSENC), .class = NV_VIDEO_ENCODE_MSENC_CLASS_ID, - .clocks = { {"msenc", UINT_MAX, 107}, {"emc", 300000000, 75} }, + .clocks = { {"msenc", UINT_MAX, 107, true}, + {"emc", 300000000, 75} }, .powergate_ids = { TEGRA_POWERGATE_MPE, -1 }, NVHOST_DEFAULT_CLOCKGATE_DELAY, .powergate_delay = 100, @@ -272,7 +274,8 @@ static struct nvhost_device_data tegra_tsec01_info = { .waitbases = BIT(NVWAITBASE_TSEC), .class = NV_TSEC_CLASS_ID, .exclusive = false, - .clocks = { {"tsec", UINT_MAX, 108}, {"emc", 300000000, 75} }, + .clocks = { {"tsec", UINT_MAX, 108, true}, + {"emc", 300000000, 75} }, NVHOST_MODULE_NO_POWERGATE_IDS, NVHOST_DEFAULT_CLOCKGATE_DELAY, .moduleid = NVHOST_MODULE_TSEC, |