diff options
| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2012-05-30 15:28:19 +0300 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-06-14 16:29:58 -0700 |
| commit | f2dd85f69f329f372db29d2e20d71f7e0e0f85bb (patch) | |
| tree | 5c5d9cc279844dc31a5b4346c4f45b9d9c9ac790 /drivers/video/tegra/host/t30 | |
| parent | 9774bbe31a0741ad71929156f59afdb2aba4eae5 (diff) | |
video: tegra: host: Parametrize host1x
Add parameters in host1x nvhost_device on
* number of sync points
* number of wait bases
* number of channels
* number of mlocks
* client managed bitmask
* naming of sync points
Add automatically generated headers and use symbols from them to
access hardware.
Move host1x device definition from generic host1x to SoC specific
source files t20.c and t30.c.
Bug 982965
Change-Id: Ibec84be22d75b363900d10bcbd59d4d8321d54a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/104974
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/host/t30')
| -rw-r--r-- | drivers/video/tegra/host/t30/t30.c | 65 |
1 files changed, 59 insertions, 6 deletions
diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c index acd5d928b1a1..9f43036c8523 100644 --- a/drivers/video/tegra/host/t30/t30.c +++ b/drivers/video/tegra/host/t30/t30.c @@ -47,10 +47,62 @@ #define NVMODMUTEX_VI (8) #define NVMODMUTEX_DSI (9) -#define T30_NVHOST_NUMCHANNELS (NV_HOST1X_CHANNELS - 1) - static int t30_num_alloc_channels = 0; +static struct resource tegra_host1x01_resources[] = { + { + .start = TEGRA_HOST1X_BASE, + .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SYNCPT_THRESH_BASE, + .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_HOST1X_MPCORE_GENERAL, + .end = INT_HOST1X_MPCORE_GENERAL, + .flags = IORESOURCE_IRQ, + }, +}; + +static const char *s_syncpt_names[32] = { + "gfx_host", + "", "", "", "", "", "", "", + "disp0_a", "disp1_a", "avp_0", + "csi_vi_0", "csi_vi_1", + "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4", + "2d_0", "2d_1", + "disp0_b", "disp1_b", + "3d", + "mpe", + "disp0_c", "disp1_c", + "vblank0", "vblank1", + "mpe_ebm_eof", "mpe_wr_safe", + "2d_tinyblt", + "dsi" +}; + +static struct host1x_device_info host1x01_info = { + .nb_channels = 8, + .nb_pts = 32, + .nb_mlocks = 16, + .nb_bases = 8, + .syncpt_names = s_syncpt_names, + .client_managed = NVSYNCPTS_CLIENT_MANAGED, +}; + +static struct nvhost_device tegra_host1x01_device = { + .dev = {.platform_data = &host1x01_info}, + .name = "host1x", + .id = -1, + .resource = tegra_host1x01_resources, + .num_resources = ARRAY_SIZE(tegra_host1x01_resources), + .clocks = {{"host1x", UINT_MAX}, {} }, + NVHOST_MODULE_NO_POWERGATE_IDS, +}; + static struct nvhost_device tegra_display01_device = { .name = "display", .id = -1, @@ -226,7 +278,6 @@ static inline int t30_nvhost_hwctx_handler_init(struct nvhost_channel *ch) static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx) { - p += NV_HOST1X_CHANNEL0_BASE; p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES; return p; } @@ -265,10 +316,12 @@ static void t30_free_nvhost_channel(struct nvhost_channel *ch) nvhost_free_channel_internal(ch, &t30_num_alloc_channels); } -static struct nvhost_channel *t30_alloc_nvhost_channel(int chindex) +static struct nvhost_channel *t30_alloc_nvhost_channel( + struct nvhost_device *dev) { - return nvhost_alloc_channel_internal(chindex, - T30_NVHOST_NUMCHANNELS, &t30_num_alloc_channels); + return nvhost_alloc_channel_internal(dev->index, + nvhost_get_host(dev)->info.nb_channels, + &t30_num_alloc_channels); } int nvhost_init_t30_support(struct nvhost_master *host, |