video: tegra: host: Parametrize host1x

Add parameters in host1x nvhost_device on
* number of sync points
* number of wait bases
* number of channels
* number of mlocks
* client managed bitmask
* naming of sync points

Add automatically generated headers and use symbols from them to
access hardware.

Move host1x device definition from generic host1x to SoC specific
source files t20.c and t30.c.

Bug 982965

Change-Id: Ibec84be22d75b363900d10bcbd59d4d8321d54a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/104974
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

26 files changed, 1535 insertions, 439 deletions

diff --git a/drivers/video/tegra/host/bus_client.c b/drivers/video/tegra/host/bus_client.c
index d72b5dff84f2..0137793b39ee 100644
--- a/drivers/video/tegra/host/bus_client.c
+++ b/drivers/video/tegra/host/bus_client.c
@@ -582,7 +582,7 @@ int nvhost_client_device_init(struct nvhost_device *dev)
 	struct nvhost_master *nvhost_master = nvhost_get_host(dev);
 	struct nvhost_channel *ch;
 
-	ch = nvhost_alloc_channel(dev->index);
+	ch = nvhost_alloc_channel(dev);
 	if (ch == NULL)
 		return -ENODEV;
 
diff --git a/drivers/video/tegra/host/chip_support.h b/drivers/video/tegra/host/chip_support.h
index 6d378183e6e5..c6860e611550 100644
--- a/drivers/video/tegra/host/chip_support.h
+++ b/drivers/video/tegra/host/chip_support.h
@@ -40,6 +40,7 @@ struct nvhost_job;
 struct nvhost_intr_syncpt;
 struct mem_handle;
 struct mem_mgr;
+struct nvhost_device;
 
 struct nvhost_chip_support {
 	struct {
@@ -67,7 +68,8 @@ struct nvhost_chip_support {
 					 u32 getptr,
 					 u32 syncpt_incrs,
 					 u32 syncval,
-					 u32 nr_slots);
+					 u32 nr_slots,
+					 u32 waitbases);
 	} cdma;
 
 	struct {
@@ -128,7 +130,8 @@ struct nvhost_chip_support {
 	} intr;
 
 	struct {
-		struct nvhost_channel *(*alloc_nvhost_channel)(int chid);
+		struct nvhost_channel *(*alloc_nvhost_channel)(
+				struct nvhost_device *dev);
 		void (*free_nvhost_channel)(struct nvhost_channel *ch);
 	} nvhost_dev;
 
diff --git a/drivers/video/tegra/host/debug.c b/drivers/video/tegra/host/debug.c
index 820eac85521d..58f9348b84bd 100644
--- a/drivers/video/tegra/host/debug.c
+++ b/drivers/video/tegra/host/debug.c
@@ -78,7 +78,7 @@ static void show_syncpts(struct nvhost_master *m, struct output *o)
 	int i;
 	BUG_ON(!nvhost_get_chip_ops()->syncpt.name);
 	nvhost_debug_output(o, "---- syncpts ----\n");
-	for (i = 0; i < m->syncpt.nb_pts; i++) {
+	for (i = 0; i < nvhost_syncpt_nb_pts(&m->syncpt); i++) {
 		u32 max = nvhost_syncpt_read_max(&m->syncpt, i);
 		u32 min = nvhost_syncpt_update_min(&m->syncpt, i);
 		if (!min && !max)
@@ -88,7 +88,7 @@ static void show_syncpts(struct nvhost_master *m, struct output *o)
 				min, max);
 	}
 
-	for (i = 0; i < m->syncpt.nb_bases; i++) {
+	for (i = 0; i < nvhost_syncpt_nb_pts(&m->syncpt); i++) {
 		u32 base_val;
 		base_val = nvhost_syncpt_read_wait_base(&m->syncpt, i);
 		if (base_val)
diff --git a/drivers/video/tegra/host/gr3d/gr3d.c b/drivers/video/tegra/host/gr3d/gr3d.c
index d586e26f104d..1ea4414c2cfb 100644
--- a/drivers/video/tegra/host/gr3d/gr3d.c
+++ b/drivers/video/tegra/host/gr3d/gr3d.c
@@ -40,7 +40,7 @@ void nvhost_3dctx_restore_begin(struct host1x_hwctx_handler *p, u32 *ptr)
 {
 	/* set class to host */
 	ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+					host1x_uclass_incr_syncpt_base_r(), 1);
 	/* increment sync point base */
 	ptr[1] = nvhost_class_host_incr_syncpt_base(p->waitbase,
 			p->restore_incrs);
@@ -66,7 +66,7 @@ void nvhost_3dctx_restore_end(struct host1x_hwctx_handler *p, u32 *ptr)
 {
 	/* syncpt increment to track restore gather. */
 	ptr[0] = nvhost_opcode_imm_incr_syncpt(
-			NV_SYNCPT_OP_DONE, p->syncpt);
+			host1x_uclass_incr_syncpt_cond_op_done_v(), p->syncpt);
 }
 
 /*** ctx3d ***/
@@ -147,7 +147,13 @@ void nvhost_3dctx_put(struct nvhost_hwctx *ctx)
 
 int nvhost_gr3d_prepare_power_off(struct nvhost_device *dev)
 {
-	return host1x_save_context(dev, NVSYNCPT_3D);
+	struct nvhost_hwctx *cur_ctx = dev->channel->cur_ctx;
+	int err = 0;
+	if (cur_ctx)
+		err = host1x_save_context(dev,
+			to_host1x_hwctx_handler(cur_ctx->h)->syncpt);
+
+	return err;
 }
 
 enum gr3d_ip_ver {
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.c b/drivers/video/tegra/host/gr3d/gr3d_t20.c
index 272c955d7e7f..88bb2be6b8a9 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t20.c
+++ b/drivers/video/tegra/host/gr3d/gr3d_t20.c
@@ -150,24 +150,26 @@ static void __init save_begin_v0(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* 3d: when done, increment syncpt to base+1 */
 	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
-	ptr[1] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+	ptr[1] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(),
 			h->syncpt); /*  incr 1 */
 	/* host: wait for syncpt base+1 */
 	ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+					host1x_uclass_wait_syncpt_base_r(), 1);
 	ptr[3] = nvhost_class_host_wait_syncpt_base(h->syncpt,
 						h->waitbase, 1);
 	/* host: signal context read thread to start reading */
-	ptr[4] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+	ptr[4] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_immediate_v(),
 			h->syncpt); /* incr 2 */
 }
 
 static void __init save_direct_v0(u32 *ptr, u32 start_reg, u32 count)
 {
-	ptr[0] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDOFF, 1);
+	ptr[0] = nvhost_opcode_nonincr(host1x_uclass_indoff_r(), 1);
 	ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
 						start_reg, true);
-	ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+	ptr[2] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_indirect_v0(u32 *ptr, u32 offset_reg, u32 offset,
@@ -177,21 +179,21 @@ static void __init save_indirect_v0(u32 *ptr, u32 offset_reg, u32 offset,
 					offset_reg, 1);
 	ptr[1] = offset;
 	ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INDOFF, 1);
+					host1x_uclass_indoff_r(), 1);
 	ptr[3] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
 						data_reg, false);
-	ptr[4] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+	ptr[4] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_end_v0(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* Wait for context read service to finish (cpu incr 3) */
-	ptr[0] = nvhost_opcode_nonincr(NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+	ptr[0] = nvhost_opcode_nonincr(host1x_uclass_wait_syncpt_base_r(), 1);
 	ptr[1] = nvhost_class_host_wait_syncpt_base(h->syncpt,
 			h->waitbase, h->save_incrs);
 	/* Advance syncpoint base */
-	ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
-	ptr[3] = nvhost_class_host_incr_syncpt_base(NVWAITBASE_3D,
+	ptr[2] = nvhost_opcode_nonincr(host1x_uclass_incr_syncpt_base_r(), 1);
+	ptr[3] = nvhost_class_host_incr_syncpt_base(h->waitbase,
 			h->save_incrs);
 	/* set class back to the unit */
 	ptr[4] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.c b/drivers/video/tegra/host/gr3d/gr3d_t30.c
index 2af8079250ac..efff61304d20 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t30.c
+++ b/drivers/video/tegra/host/gr3d/gr3d_t30.c
@@ -116,11 +116,12 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
 	/* wait for 3d idle */
 	nvhost_cdma_push(cdma,
 			nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
-			nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
-					p->syncpt));
+			nvhost_opcode_imm_incr_syncpt(
+				host1x_uclass_incr_syncpt_cond_op_done_v(),
+				p->syncpt));
 	nvhost_cdma_push(cdma,
 			nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+					host1x_uclass_wait_syncpt_base_r(), 1),
 			nvhost_class_host_wait_syncpt_base(p->syncpt,
 							p->waitbase, 1));
 	/* back to 3d */
@@ -168,11 +169,11 @@ static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count)
 	nvhost_3dctx_restore_direct(ptr + 1, start_reg, count);
 	ptr += RESTORE_DIRECT_SIZE;
 	ptr[1] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INDOFF, 1);
+					host1x_uclass_indoff_r(), 1);
 	ptr[2] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
 						start_reg, true);
 	/* TODO could do this in the setclass if count < 6 */
-	ptr[3] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+	ptr[3] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
@@ -186,10 +187,10 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
 	ptr += RESTORE_INDIRECT_SIZE;
 	ptr[2] = nvhost_opcode_imm(offset_reg, offset);
 	ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INDOFF, 1);
+					host1x_uclass_indoff_r(), 1);
 	ptr[4] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
 						data_reg, false);
-	ptr[5] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+	ptr[5] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
@@ -203,13 +204,14 @@ static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
 	ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
 			(1 << register_sets) - 1);
 	/* op_done syncpt incr to flush FDC */
-	ptr[2] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, p->syncpt);
+	ptr[2] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(), p->syncpt);
 	/* host wait for that syncpt incr, and advance the wait base */
 	ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-			NV_CLASS_HOST_WAIT_SYNCPT_BASE,
+			host1x_uclass_wait_syncpt_base_r(),
 			nvhost_mask2(
-					NV_CLASS_HOST_WAIT_SYNCPT_BASE,
-					NV_CLASS_HOST_INCR_SYNCPT_BASE));
+				host1x_uclass_wait_syncpt_base_r(),
+				host1x_uclass_incr_syncpt_base_r()));
 	ptr[4] = nvhost_class_host_wait_syncpt_base(p->syncpt,
 				p->waitbase, p->save_incrs - 1);
 	ptr[5] = nvhost_class_host_incr_syncpt_base(p->waitbase,
diff --git a/drivers/video/tegra/host/host1x/host1x.c b/drivers/video/tegra/host/host1x/host1x.c
index d203bc73a67d..33ebc1ff5d22 100644
--- a/drivers/video/tegra/host/host1x/host1x.c
+++ b/drivers/video/tegra/host/host1x/host1x.c
@@ -19,29 +19,20 @@
  */
 
 #include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
 #include <linux/fs.h>
 #include <linux/cdev.h>
 #include <linux/uaccess.h>
 #include <linux/file.h>
 #include <linux/clk.h>
-#include <linux/hrtimer.h>
 
 #include "dev.h"
 #include "bus.h"
 #include <trace/events/nvhost.h>
 
-#include <linux/io.h>
-
 #include <linux/nvhost.h>
 #include <linux/nvhost_ioctl.h>
-#include <mach/hardware.h>
-#include <mach/iomap.h>
 
 #include "debug.h"
-#include "t20/t20.h"
-#include "t30/t30.h"
 #include "bus_client.h"
 #include "nvhost_acm.h"
 #include "nvhost_channel.h"
@@ -49,33 +40,6 @@
 
 #define DRIVER_NAME		"host1x"
 
-static struct resource tegra_host1x01_resources[] = {
-	{
-		.start = TEGRA_HOST1X_BASE,
-		.end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = INT_SYNCPT_THRESH_BASE,
-		.end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = INT_HOST1X_MPCORE_GENERAL,
-		.end = INT_HOST1X_MPCORE_GENERAL,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct nvhost_device tegra_host1x01_device = {
-	.name		= "host1x",
-	.id		= -1,
-	.resource	= tegra_host1x01_resources,
-	.num_resources	= ARRAY_SIZE(tegra_host1x01_resources),
-	.clocks		= {{"host1x", UINT_MAX}, {} },
-	NVHOST_MODULE_NO_POWERGATE_IDS,
-};
-
 struct nvhost_ctrl_userctx {
 	struct nvhost_master *dev;
 	u32 *mod_locks;
@@ -91,7 +55,7 @@ static int nvhost_ctrlrelease(struct inode *inode, struct file *filp)
 	filp->private_data = NULL;
 	if (priv->mod_locks[0])
 		nvhost_module_idle(priv->dev->dev);
-	for (i = 1; i < priv->dev->syncpt.nb_mlocks; i++)
+	for (i = 1; i < nvhost_syncpt_nb_mlocks(&priv->dev->syncpt); i++)
 		if (priv->mod_locks[i])
 			nvhost_mutex_unlock(&priv->dev->syncpt, i);
 	kfree(priv->mod_locks);
@@ -109,7 +73,9 @@ static int nvhost_ctrlopen(struct inode *inode, struct file *filp)
 	trace_nvhost_ctrlopen(host->dev->name);
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	mod_locks = kzalloc(sizeof(u32) * host->syncpt.nb_mlocks, GFP_KERNEL);
+	mod_locks = kzalloc(sizeof(u32)
+			* nvhost_syncpt_nb_mlocks(&host->syncpt),
+			GFP_KERNEL);
 
 	if (!(priv && mod_locks)) {
 		kfree(priv);
@@ -126,7 +92,7 @@ static int nvhost_ctrlopen(struct inode *inode, struct file *filp)
 static int nvhost_ioctl_ctrl_syncpt_read(struct nvhost_ctrl_userctx *ctx,
 	struct nvhost_ctrl_syncpt_read_args *args)
 {
-	if (args->id >= ctx->dev->syncpt.nb_pts)
+	if (args->id >= nvhost_syncpt_nb_pts(&ctx->dev->syncpt))
 		return -EINVAL;
 	args->value = nvhost_syncpt_read(&ctx->dev->syncpt, args->id);
 	trace_nvhost_ioctl_ctrl_syncpt_read(args->id, args->value);
@@ -136,7 +102,7 @@ static int nvhost_ioctl_ctrl_syncpt_read(struct nvhost_ctrl_userctx *ctx,
 static int nvhost_ioctl_ctrl_syncpt_incr(struct nvhost_ctrl_userctx *ctx,
 	struct nvhost_ctrl_syncpt_incr_args *args)
 {
-	if (args->id >= ctx->dev->syncpt.nb_pts)
+	if (args->id >= nvhost_syncpt_nb_pts(&ctx->dev->syncpt))
 		return -EINVAL;
 	trace_nvhost_ioctl_ctrl_syncpt_incr(args->id);
 	nvhost_syncpt_incr(&ctx->dev->syncpt, args->id);
@@ -148,7 +114,7 @@ static int nvhost_ioctl_ctrl_syncpt_waitex(struct nvhost_ctrl_userctx *ctx,
 {
 	u32 timeout;
 	int err;
-	if (args->id >= ctx->dev->syncpt.nb_pts)
+	if (args->id >= nvhost_syncpt_nb_pts(&ctx->dev->syncpt))
 		return -EINVAL;
 	if (args->timeout == NVHOST_NO_TIMEOUT)
 		timeout = MAX_SCHEDULE_TIMEOUT;
@@ -167,7 +133,7 @@ static int nvhost_ioctl_ctrl_module_mutex(struct nvhost_ctrl_userctx *ctx,
 	struct nvhost_ctrl_module_mutex_args *args)
 {
 	int err = 0;
-	if (args->id >= ctx->dev->syncpt.nb_mlocks ||
+	if (args->id >= nvhost_syncpt_nb_mlocks(&ctx->dev->syncpt) ||
 	    args->lock > 1)
 		return -EINVAL;
 
@@ -377,10 +343,10 @@ fail:
 	return err;
 }
 
-struct nvhost_channel *nvhost_alloc_channel(int index)
+struct nvhost_channel *nvhost_alloc_channel(struct nvhost_device *dev)
 {
 	BUG_ON(!host_device_op().alloc_nvhost_channel);
-	return host_device_op().alloc_nvhost_channel(index);
+	return host_device_op().alloc_nvhost_channel(dev);
 }
 
 void nvhost_free_channel(struct nvhost_channel *ch)
@@ -404,7 +370,8 @@ static int __devinit nvhost_alloc_resources(struct nvhost_master *host)
 		return err;
 
 	host->intr.syncpt = kzalloc(sizeof(struct nvhost_intr_syncpt) *
-				    host->syncpt.nb_pts, GFP_KERNEL);
+				    nvhost_syncpt_nb_pts(&host->syncpt),
+				    GFP_KERNEL);
 
 	if (!host->intr.syncpt) {
 		/* frees happen in the support removal phase */
@@ -434,6 +401,13 @@ static int __devinit nvhost_probe(struct nvhost_device *dev,
 	if (!host)
 		return -ENOMEM;
 
+	/*  Register host1x device as bus master */
+	host->dev = dev;
+
+	/* Copy host1x parameters */
+	memcpy(&host->info, dev->dev.platform_data,
+			sizeof(struct host1x_device_info));
+
 	host->reg_mem = request_mem_region(regs->start,
 					resource_size(regs), dev->name);
 	if (!host->reg_mem) {
diff --git a/drivers/video/tegra/host/host1x/host1x.h b/drivers/video/tegra/host/host1x/host1x.h
index 295d3ff4c7f4..c602a347f7f9 100644
--- a/drivers/video/tegra/host/host1x/host1x.h
+++ b/drivers/video/tegra/host/host1x/host1x.h
@@ -18,8 +18,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __NVHOST_DEV_H
-#define __NVHOST_DEV_H
+#ifndef __NVHOST_HOST1X_H
+#define __NVHOST_HOST1X_H
 
 #include <linux/cdev.h>
 #include "nvhost_syncpt.h"
@@ -28,9 +28,18 @@
 #define TRACE_MAX_LENGTH	128U
 #define IFACE_NAME		"nvhost"
 
-struct nvhost_hwctx;
 struct nvhost_channel;
 struct mem_mgr;
+struct nvhost_device;
+
+struct host1x_device_info {
+	int		nb_channels;	/* host1x: num channels supported */
+	int		nb_pts;	/* host1x: num syncpoints supported */
+	int		nb_bases;	/* host1x: num syncpoints supported */
+	u32		client_managed; /* host1x: client managed syncpts */
+	int		nb_mlocks;	/* host1x: number of mlocks */
+	const char	**syncpt_names;	/* names of sync points */
+};
 
 struct nvhost_master {
 	void __iomem *aperture;
@@ -44,6 +53,8 @@ struct nvhost_master {
 	struct nvhost_intr intr;
 	struct nvhost_device *dev;
 	atomic_t clientid;
+
+	struct host1x_device_info info;
 };
 
 extern struct nvhost_master *nvhost;
@@ -51,13 +62,9 @@ extern struct nvhost_master *nvhost;
 void nvhost_debug_init(struct nvhost_master *master);
 void nvhost_debug_dump(struct nvhost_master *master);
 
-struct nvhost_channel *nvhost_alloc_channel(int index);
+struct nvhost_channel *nvhost_alloc_channel(struct nvhost_device *dev);
 void nvhost_free_channel(struct nvhost_channel *ch);
 
 extern pid_t nvhost_debug_null_kickoff_pid;
 
-struct nvhost_device;
-
-extern struct nvhost_device tegra_host1x01_device;
-
 #endif
diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.c b/drivers/video/tegra/host/host1x/host1x_cdma.c
index 00289fc6d980..7a01cca3be4b 100644
--- a/drivers/video/tegra/host/host1x/host1x_cdma.c
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.c
@@ -33,9 +33,9 @@
 
 static inline u32 host1x_channel_dmactrl(int stop, int get_rst, int init_get)
 {
-	return HOST1X_CREATE(CHANNEL_DMACTRL, DMASTOP, stop)
-			| HOST1X_CREATE(CHANNEL_DMACTRL, DMAGETRST, get_rst)
-			| HOST1X_CREATE(CHANNEL_DMACTRL, DMAINITGET, init_get);
+	return host1x_channel_dmactrl_dmastop_f(stop)
+		| host1x_channel_dmactrl_dmagetrst_f(get_rst)
+		| host1x_channel_dmactrl_dmainitget_f(init_get);
 }
 
 static void cdma_timeout_handler(struct work_struct *work);
@@ -222,7 +222,8 @@ static void cdma_timeout_destroy(struct nvhost_cdma *cdma)
  * Increment timedout buffer's syncpt via CPU.
  */
 static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
-				u32 syncpt_incrs, u32 syncval, u32 nr_slots)
+				u32 syncpt_incrs, u32 syncval, u32 nr_slots,
+				u32 waitbases)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
 	struct push_buffer *pb = &cdma->push_buffer;
@@ -235,10 +236,10 @@ static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
 	nvhost_syncpt_update_min(&dev->syncpt, cdma->timeout.syncpt_id);
 
 	/* update WAITBASE_3D by same number of incrs */
-	if (cdma->timeout.syncpt_id == NVSYNCPT_3D) {
+	if (waitbases) {
 		void __iomem *p;
-		p = dev->sync_aperture + HOST1X_SYNC_SYNCPT_BASE_0 +
-				(NVWAITBASE_3D * sizeof(u32));
+		p = dev->sync_aperture + host1x_sync_syncpt_base_0_r() +
+				(ffs(waitbases) * sizeof(u32));
 		writel(syncval, p);
 	}
 
@@ -269,20 +270,20 @@ static void cdma_start(struct nvhost_cdma *cdma)
 	cdma->last_put = cdma_pb_op().putptr(&cdma->push_buffer);
 
 	writel(host1x_channel_dmactrl(true, false, false),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	/* set base, put, end pointer (all of memory) */
-	writel(0, chan_regs + HOST1X_CHANNEL_DMASTART);
-	writel(cdma->last_put, chan_regs + HOST1X_CHANNEL_DMAPUT);
-	writel(0xFFFFFFFF, chan_regs + HOST1X_CHANNEL_DMAEND);
+	writel(0, chan_regs + host1x_channel_dmastart_r());
+	writel(cdma->last_put, chan_regs + host1x_channel_dmaput_r());
+	writel(0xFFFFFFFF, chan_regs + host1x_channel_dmaend_r());
 
 	/* reset GET */
 	writel(host1x_channel_dmactrl(true, true, true),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	/* start the command DMA */
 	writel(host1x_channel_dmactrl(false, false, false),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	cdma->running = true;
 }
@@ -304,32 +305,32 @@ static void cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 	cdma->last_put = cdma_pb_op().putptr(&cdma->push_buffer);
 
 	writel(host1x_channel_dmactrl(true, false, false),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	/* set base, end pointer (all of memory) */
-	writel(0, chan_regs + HOST1X_CHANNEL_DMASTART);
-	writel(0xFFFFFFFF, chan_regs + HOST1X_CHANNEL_DMAEND);
+	writel(0, chan_regs + host1x_channel_dmastart_r());
+	writel(0xFFFFFFFF, chan_regs + host1x_channel_dmaend_r());
 
 	/* set GET, by loading the value in PUT (then reset GET) */
-	writel(getptr, chan_regs + HOST1X_CHANNEL_DMAPUT);
+	writel(getptr, chan_regs + host1x_channel_dmaput_r());
 	writel(host1x_channel_dmactrl(true, true, true),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	dev_dbg(&dev->dev->dev,
 		"%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n",
 		__func__,
-		readl(chan_regs + HOST1X_CHANNEL_DMAGET),
-		readl(chan_regs + HOST1X_CHANNEL_DMAPUT),
+		readl(chan_regs + host1x_channel_dmaget_r()),
+		readl(chan_regs + host1x_channel_dmaput_r()),
 		cdma->last_put);
 
 	/* deassert GET reset and set PUT */
 	writel(host1x_channel_dmactrl(true, false, false),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
-	writel(cdma->last_put, chan_regs + HOST1X_CHANNEL_DMAPUT);
+		chan_regs + host1x_channel_dmactrl_r());
+	writel(cdma->last_put, chan_regs + host1x_channel_dmaput_r());
 
 	/* start the command DMA */
 	writel(host1x_channel_dmactrl(false, false, false),
-		chan_regs + HOST1X_CHANNEL_DMACTRL);
+		chan_regs + host1x_channel_dmactrl_r());
 
 	cdma->running = true;
 }
@@ -347,7 +348,7 @@ static void cdma_kick(struct nvhost_cdma *cdma)
 	if (put != cdma->last_put) {
 		void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
 		wmb();
-		writel(put, chan_regs + HOST1X_CHANNEL_DMAPUT);
+		writel(put, chan_regs + host1x_channel_dmaput_r());
 		cdma->last_put = put;
 	}
 }
@@ -360,7 +361,7 @@ static void cdma_stop(struct nvhost_cdma *cdma)
 	if (cdma->running) {
 		nvhost_cdma_wait_locked(cdma, CDMA_EVENT_SYNC_QUEUE_EMPTY);
 		writel(host1x_channel_dmactrl(true, false, false),
-			chan_regs + HOST1X_CHANNEL_DMACTRL);
+			chan_regs + host1x_channel_dmactrl_r());
 		cdma->running = false;
 	}
 	mutex_unlock(&cdma->lock);
@@ -395,21 +396,21 @@ void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 	dev_dbg(&dev->dev->dev,
 		"begin channel teardown (channel id %d)\n", ch->chid);
 
-	cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	cmdproc_stop = readl(dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 	cmdproc_stop |= BIT(ch->chid);
-	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	writel(cmdproc_stop, dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 
 	dev_dbg(&dev->dev->dev,
 		"%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n",
 		__func__,
-		readl(ch->aperture + HOST1X_CHANNEL_DMAGET),
-		readl(ch->aperture + HOST1X_CHANNEL_DMAPUT),
+		readl(ch->aperture + host1x_channel_dmaget_r()),
+		readl(ch->aperture + host1x_channel_dmaput_r()),
 		cdma->last_put);
 
 	writel(host1x_channel_dmactrl(true, false, false),
-		ch->aperture + HOST1X_CHANNEL_DMACTRL);
+		ch->aperture + host1x_channel_dmactrl_r());
 
-	writel(BIT(ch->chid), dev->sync_aperture + HOST1X_SYNC_CH_TEARDOWN);
+	writel(BIT(ch->chid), dev->sync_aperture + host1x_sync_ch_teardown_r());
 	nvhost_module_reset(ch->dev);
 
 	cdma->running = false;
@@ -428,9 +429,9 @@ void cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
 		"end channel teardown (id %d, DMAGET restart = 0x%x)\n",
 		ch->chid, getptr);
 
-	cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	cmdproc_stop = readl(dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 	cmdproc_stop &= ~(BIT(ch->chid));
-	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	writel(cmdproc_stop, dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 
 	cdma->torndown = false;
 	cdma_timeout_restart(cdma, getptr);
@@ -468,9 +469,9 @@ static void cdma_timeout_handler(struct work_struct *work)
 	}
 
 	/* stop processing to get a clean snapshot */
-	prev_cmdproc = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	prev_cmdproc = readl(dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 	cmdproc_stop = prev_cmdproc | BIT(ch->chid);
-	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+	writel(cmdproc_stop, dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 
 	dev_dbg(&dev->dev->dev, "cdma_timeout: cmdproc was 0x%x is 0x%x\n",
 		prev_cmdproc, cmdproc_stop);
@@ -485,7 +486,7 @@ static void cdma_timeout_handler(struct work_struct *work)
 		/* restore */
 		cmdproc_stop = prev_cmdproc & ~(BIT(ch->chid));
 		writel(cmdproc_stop,
-			dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+			dev->sync_aperture + host1x_sync_cmdproc_stop_r());
 		mutex_unlock(&cdma->lock);
 		return;
 	}
@@ -501,7 +502,7 @@ static void cdma_timeout_handler(struct work_struct *work)
 	/* stop HW, resetting channel/module */
 	cdma_op().timeout_teardown_begin(cdma);
 
-	nvhost_cdma_update_sync_queue(cdma, sp, &dev->dev->dev);
+	nvhost_cdma_update_sync_queue(cdma, sp, dev->dev);
 	mutex_unlock(&cdma->lock);
 }
 
diff --git a/drivers/video/tegra/host/host1x/host1x_channel.c b/drivers/video/tegra/host/host1x/host1x_channel.c
index 4b167a3753a1..03ba72ca46a0 100644
--- a/drivers/video/tegra/host/host1x/host1x_channel.c
+++ b/drivers/video/tegra/host/host1x/host1x_channel.c
@@ -42,7 +42,7 @@ static void sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val)
 		waitbase = find_first_bit(&waitbase_mask, BITS_PER_LONG);
 		nvhost_cdma_push(&ch->cdma,
 			nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-				NV_CLASS_HOST_LOAD_SYNCPT_BASE,
+				host1x_uclass_load_syncpt_base_r(),
 				1),
 				nvhost_class_host_load_syncpt_base(waitbase,
 						syncpt_val));
@@ -158,7 +158,8 @@ void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs)
 	u32 op_incr;
 
 	/* push increments that correspond to nulled out commands */
-	op_incr = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+	op_incr = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(),
 			job->syncpt_id);
 	for (incr = 0; incr < (user_syncpt_incrs >> 1); incr++)
 		nvhost_cdma_push(&ch->cdma, op_incr, op_incr);
@@ -171,7 +172,7 @@ void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs)
 		nvhost_cdma_push(&ch->cdma,
 			nvhost_opcode_setclass(
 				NV_HOST1X_CLASS_ID,
-				NV_CLASS_HOST_INCR_SYNCPT_BASE,
+				host1x_uclass_incr_syncpt_base_r(),
 				1),
 			nvhost_class_host_incr_syncpt_base(
 				waitbase,
@@ -386,38 +387,41 @@ int host1x_channel_read_3d_reg(
 	/* Switch to 3D - wait for it to complete what it was doing */
 	nvhost_cdma_push(&channel->cdma,
 		nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
-		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+		nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(),
 			p->syncpt));
 	nvhost_cdma_push(&channel->cdma,
 		nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-			NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+			host1x_uclass_wait_syncpt_base_r(), 1),
 		nvhost_class_host_wait_syncpt_base(p->syncpt,
 			p->waitbase, 1));
 	/*  Tell 3D to send register value to FIFO */
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_nonincr(NV_CLASS_HOST_INDOFF, 1),
+		nvhost_opcode_nonincr(host1x_uclass_indoff_r(), 1),
 		nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
 			offset, false));
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_imm(NV_CLASS_HOST_INDDATA, 0),
+		nvhost_opcode_imm(host1x_uclass_inddata_r(), 0),
 		NVHOST_OPCODE_NOOP);
 	/*  Increment syncpt to indicate that FIFO can be read */
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+		nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_immediate_v(),
 			p->syncpt),
 		NVHOST_OPCODE_NOOP);
 	/*  Wait for value to be read from FIFO */
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_nonincr(NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+		nvhost_opcode_nonincr(host1x_uclass_wait_syncpt_base_r(), 1),
 		nvhost_class_host_wait_syncpt_base(p->syncpt,
 			p->waitbase, 3));
 	/*  Indicate submit complete */
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1),
+		nvhost_opcode_nonincr(host1x_uclass_incr_syncpt_base_r(), 1),
 		nvhost_class_host_incr_syncpt_base(p->waitbase, 4));
 	nvhost_cdma_push(&channel->cdma,
 		NVHOST_OPCODE_NOOP,
-		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+		nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_immediate_v(),
 			p->syncpt));
 
 	/* end CDMA submit  */
@@ -492,8 +496,8 @@ int host1x_drain_read_fifo(void __iomem *chan_regs,
 
 		while (!entries && time_before(jiffies, timeout)) {
 			/* query host for number of entries in fifo */
-			entries = HOST1X_VAL(CHANNEL_FIFOSTAT, OUTFENTRIES,
-				readl(chan_regs + HOST1X_CHANNEL_FIFOSTAT));
+			entries = host1x_channel_fifostat_outfentries_v(
+				readl(chan_regs + host1x_channel_fifostat_r()));
 			if (!entries)
 				cpu_relax();
 		}
@@ -508,16 +512,16 @@ int host1x_drain_read_fifo(void __iomem *chan_regs,
 
 		while (num & ~0x3) {
 			u32 arr[4];
-			arr[0] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
-			arr[1] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
-			arr[2] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
-			arr[3] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+			arr[0] = readl(chan_regs + host1x_channel_inddata_r());
+			arr[1] = readl(chan_regs + host1x_channel_inddata_r());
+			arr[2] = readl(chan_regs + host1x_channel_inddata_r());
+			arr[3] = readl(chan_regs + host1x_channel_inddata_r());
 			memcpy(ptr, arr, 4*sizeof(u32));
 			ptr += 4;
 			num -= 4;
 		}
 		while (num--)
-			*ptr++ = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+			*ptr++ = readl(chan_regs + host1x_channel_inddata_r());
 	}
 	*pending = entries;
 
diff --git a/drivers/video/tegra/host/host1x/host1x_debug.c b/drivers/video/tegra/host/host1x/host1x_debug.c
index 3b14aeeae153..dc23ba6fb704 100644
--- a/drivers/video/tegra/host/host1x/host1x_debug.c
+++ b/drivers/video/tegra/host/host1x/host1x_debug.c
@@ -283,17 +283,17 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 	u32 cbstat, cbread;
 	u32 val, base, baseval;
 
-	dmaput = readl(channel->aperture + HOST1X_CHANNEL_DMAPUT);
-	dmaget = readl(channel->aperture + HOST1X_CHANNEL_DMAGET);
-	dmactrl = readl(channel->aperture + HOST1X_CHANNEL_DMACTRL);
-	cbread = readl(m->sync_aperture + HOST1X_SYNC_CBREAD_x(chid));
-	cbstat = readl(m->sync_aperture + HOST1X_SYNC_CBSTAT_x(chid));
+	dmaput = readl(channel->aperture + host1x_channel_dmaput_r());
+	dmaget = readl(channel->aperture + host1x_channel_dmaget_r());
+	dmactrl = readl(channel->aperture + host1x_channel_dmactrl_r());
+	cbread = readl(m->sync_aperture + host1x_sync_cbread0_r() + 4 * chid);
+	cbstat = readl(m->sync_aperture + host1x_sync_cbstat_0_r() + 4 * chid);
 
 	nvhost_debug_output(o, "%d-%s (%d): ", chid,
 			    channel->dev->name,
 			    channel->dev->refcount);
 
-	if (HOST1X_VAL(CHANNEL_DMACTRL, DMASTOP, dmactrl)
+	if (host1x_channel_dmactrl_dmastop_v(dmactrl)
 		|| !channel->cdma.push_buffer.mapped) {
 		nvhost_debug_output(o, "inactive\n\n");
 		return;
@@ -307,9 +307,8 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 
 	case 0x00010009:
 		base = (cbread >> 16) & 0xff;
-		val = readl(m->sync_aperture +
-				HOST1X_SYNC_SYNCPT_BASE_x(base));
-		baseval = HOST1X_VAL(SYNC_SYNCPT_BASE_0, BASE, val);
+		baseval = readl(m->sync_aperture +
+				host1x_sync_syncpt_base_0_r() + 4 * base);
 		val = cbread & 0xffff;
 		nvhost_debug_output(o, "waiting on syncpt %d val %d "
 			  "(base %d = %d; offset = %d)\n",
@@ -320,8 +319,8 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 	default:
 		nvhost_debug_output(o,
 				"active class %02x, offset %04x, val %08x\n",
-				HOST1X_VAL(SYNC_CBSTAT_0, CBCLASS0, cbstat),
-				HOST1X_VAL(SYNC_CBSTAT_0, CBOFFSET0, cbstat),
+				host1x_sync_cbstat_0_cbclass0_v(cbstat),
+				host1x_sync_cbstat_0_cboffset0_v(cbstat),
 				cbread);
 		break;
 	}
@@ -343,35 +342,35 @@ void t20_debug_show_channel_fifo(struct nvhost_master *m,
 
 	nvhost_debug_output(o, "%d: fifo:\n", chid);
 
-	val = readl(channel->aperture + HOST1X_CHANNEL_FIFOSTAT);
+	val = readl(channel->aperture + host1x_channel_fifostat_r());
 	nvhost_debug_output(o, "FIFOSTAT %08x\n", val);
-	if (HOST1X_VAL(CHANNEL_FIFOSTAT, CFEMPTY, val)) {
+	if (host1x_channel_fifostat_cfempty_v(val)) {
 		nvhost_debug_output(o, "[empty]\n");
 		return;
 	}
 
-	writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
-	writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
-			| HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid),
-		m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+	writel(0x0, m->sync_aperture + host1x_sync_cfpeek_ctrl_r());
+	writel(host1x_sync_cfpeek_ctrl_cfpeek_ena_f(1)
+			| host1x_sync_cfpeek_ctrl_cfpeek_channr_f(chid),
+		m->sync_aperture + host1x_sync_cfpeek_ctrl_r());
 
-	val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_PTRS);
-	rd_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_RD_PTR, val);
-	wr_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_WR_PTR, val);
+	val = readl(m->sync_aperture + host1x_sync_cfpeek_ptrs_r());
+	rd_ptr = host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(val);
+	wr_ptr = host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(val);
 
-	val = readl(m->sync_aperture + HOST1X_SYNC_CFx_SETUP(chid));
-	start = HOST1X_VAL(SYNC_CF0_SETUP, BASE, val);
-	end = HOST1X_VAL(SYNC_CF0_SETUP, LIMIT, val);
+	val = readl(m->sync_aperture + host1x_sync_cf0_setup_r() + 4 * chid);
+	start = host1x_sync_cf0_setup_cf0_base_v(val);
+	end = host1x_sync_cf0_setup_cf0_limit_v(val);
 
 	state = NVHOST_DBG_STATE_CMD;
 
 	do {
-		writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
-		writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
-				| HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid)
-				| HOST1X_CREATE(SYNC_CFPEEK_CTRL, ADDR, rd_ptr),
-			m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
-		val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_READ);
+		writel(0x0, m->sync_aperture + host1x_sync_cfpeek_ctrl_r());
+		writel(host1x_sync_cfpeek_ctrl_cfpeek_ena_f(1)
+				| host1x_sync_cfpeek_ctrl_cfpeek_channr_f(chid)
+				| host1x_sync_cfpeek_ctrl_cfpeek_addr_f(rd_ptr),
+			m->sync_aperture + host1x_sync_cfpeek_ctrl_r());
+		val = readl(m->sync_aperture + host1x_sync_cfpeek_read_r());
 
 		show_channel_word(o, &state, &count, 0, val, NULL);
 
@@ -385,21 +384,24 @@ void t20_debug_show_channel_fifo(struct nvhost_master *m,
 		nvhost_debug_output(o, ", ...])\n");
 	nvhost_debug_output(o, "\n");
 
-	writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+	writel(0x0, m->sync_aperture + host1x_sync_cfpeek_ctrl_r());
 }
 
 static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o)
 {
-	u32 __iomem *mlo_regs = m->sync_aperture + HOST1X_SYNC_MLOCK_OWNER_0;
+	u32 __iomem *mlo_regs = m->sync_aperture +
+		host1x_sync_mlock_owner_0_r();
 	int i;
 
 	nvhost_debug_output(o, "---- mlocks ----\n");
 	for (i = 0; i < NV_HOST1X_NB_MLOCKS; i++) {
 		u32 owner = readl(mlo_regs + i);
-		if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CH_OWNS, owner))
+		if (host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(owner))
 			nvhost_debug_output(o, "%d: locked by channel %d\n",
-				i, HOST1X_VAL(SYNC_MLOCK_OWNER_0, CHID, owner));
-		else if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CPU_OWNS, owner))
+				i,
+				host1x_sync_mlock_owner_0_mlock_owner_chid_0_f(
+					owner));
+		else if (host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(owner))
 			nvhost_debug_output(o, "%d: locked by cpu\n", i);
 		else
 			nvhost_debug_output(o, "%d: unlocked\n", i);
diff --git a/drivers/video/tegra/host/host1x/host1x_hardware.h b/drivers/video/tegra/host/host1x/host1x_hardware.h
index d13d57523644..357b61d42b50 100644
--- a/drivers/video/tegra/host/host1x/host1x_hardware.h
+++ b/drivers/video/tegra/host/host1x/host1x_hardware.h
@@ -23,6 +23,9 @@
 
 #include <linux/types.h>
 #include <linux/bitops.h>
+#include "hw_host1x_channel.h"
+#include "hw_host1x_sync.h"
+#include "hw_host1x_uclass.h"
 
 /* class ids */
 enum {
@@ -33,129 +36,13 @@ enum {
 
 
 /* channel registers */
-#define NV_HOST1X_CHANNELS 8
-#define NV_HOST1X_CHANNEL0_BASE 0
 #define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384
 #define NV_HOST1X_SYNC_MLOCK_NUM 16
 
-#define HOST1X_VAL(reg, field, regdata) \
-	((regdata >> HOST1X_##reg##_##field##_SHIFT) \
-			& HOST1X_##reg##_##field##_MASK)
-#define HOST1X_CREATE(reg, field, data) \
-	((data & HOST1X_##reg##_##field##_MASK) \
-			<< HOST1X_##reg##_##field##_SHIFT) \
-
-#define HOST1X_CHANNEL_FIFOSTAT		0x00
-#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_SHIFT 10
-#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_MASK 0x1
-#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_SHIFT 24
-#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_MASK 0x1f
-#define HOST1X_CHANNEL_INDDATA		0x0c
-#define HOST1X_CHANNEL_DMASTART		0x14
-#define HOST1X_CHANNEL_DMAPUT		0x18
-#define HOST1X_CHANNEL_DMAGET		0x1c
-#define HOST1X_CHANNEL_DMAEND		0x20
-#define HOST1X_CHANNEL_DMACTRL		0x24
-#define HOST1X_CHANNEL_DMACTRL_DMASTOP_SHIFT 0
-#define HOST1X_CHANNEL_DMACTRL_DMASTOP_MASK 0x1
-#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_SHIFT 1
-#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_MASK 0x1
-#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_SHIFT 2
-#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_MASK 0x1
-
-#define HOST1X_CHANNEL_SYNC_REG_BASE	0x3000
-
-#define HOST1X_SYNC_INTMASK		0x4
-#define HOST1X_SYNC_INTC0MASK		0x8
-#define HOST1X_SYNC_HINTSTATUS		0x20
-#define HOST1X_SYNC_HINTMASK		0x24
-#define HOST1X_SYNC_HINTSTATUS_EXT	0x28
-#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_SHIFT 30
-#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_MASK 0x1
-#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_SHIFT 31
-#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_MASK 0x1
-#define HOST1X_SYNC_HINTMASK_EXT	0x2c
-#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS 0x40
-#define HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS 0x48
-#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE 0x60
-#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0 0x68
-#define HOST1X_SYNC_CF0_SETUP		0x80
-#define HOST1X_SYNC_CF0_SETUP_BASE_SHIFT 0
-#define HOST1X_SYNC_CF0_SETUP_BASE_MASK	0x1ff
-#define HOST1X_SYNC_CF0_SETUP_LIMIT_SHIFT 16
-#define HOST1X_SYNC_CF0_SETUP_LIMIT_MASK 0x1ff
-#define HOST1X_SYNC_CFx_SETUP(x)	(HOST1X_SYNC_CF0_SETUP + (4 * (x)))
-
-#define HOST1X_SYNC_CMDPROC_STOP	0xac
-#define HOST1X_SYNC_CH_TEARDOWN		0xb0
-#define HOST1X_SYNC_USEC_CLK		0x1a4
-#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG	0x1a8
-#define HOST1X_SYNC_IP_BUSY_TIMEOUT	0x1bc
-#define HOST1X_SYNC_IP_READ_TIMEOUT_ADDR 0x1c0
-#define HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR 0x1c4
-#define HOST1X_SYNC_MLOCK_0		0x2c0
-#define HOST1X_SYNC_MLOCK_OWNER_0	0x340
-#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_SHIFT 8
-#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_MASK 0xf
-#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_SHIFT 1
-#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_MASK 0x1
-#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_SHIFT 0
-#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_MASK 0x1
-#define HOST1X_SYNC_SYNCPT_0		0x400
-#define HOST1X_SYNC_SYNCPT_INT_THRESH_0	0x500
-
-#define HOST1X_SYNC_SYNCPT_BASE_0	0x600
-#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_SHIFT 0
-#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_MASK 0xffff
-#define HOST1X_SYNC_SYNCPT_BASE_x(x)	(HOST1X_SYNC_SYNCPT_BASE_0 + (4 * (x)))
-
-#define HOST1X_SYNC_SYNCPT_CPU_INCR	0x700
-
-#define HOST1X_SYNC_CBREAD_0		0x720
-#define HOST1X_SYNC_CBREAD_x(x)		(HOST1X_SYNC_CBREAD_0 + (4 * (x)))
-#define HOST1X_SYNC_CFPEEK_CTRL		0x74c
-#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_SHIFT 0
-#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_MASK 0x1ff
-#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_SHIFT 16
-#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_MASK 0x7
-#define HOST1X_SYNC_CFPEEK_CTRL_ENA_SHIFT 31
-#define HOST1X_SYNC_CFPEEK_CTRL_ENA_MASK 0x1
-#define HOST1X_SYNC_CFPEEK_READ		0x750
-#define HOST1X_SYNC_CFPEEK_PTRS		0x754
-#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_SHIFT 0
-#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_MASK 0x1ff
-#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_SHIFT 16
-#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_MASK 0x1ff
-#define HOST1X_SYNC_CBSTAT_0		0x758
-#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_SHIFT 0
-#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_MASK 0xffff
-#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_SHIFT 16
-#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_MASK 0xffff
-#define HOST1X_SYNC_CBSTAT_x(x)		(HOST1X_SYNC_CBSTAT_0 + (4 * (x)))
-
 /* sync registers */
-#define NV_HOST1X_SYNCPT_NB_PTS 32
-#define NV_HOST1X_SYNCPT_NB_BASES 8
+#define HOST1X_CHANNEL_SYNC_REG_BASE   0x3000
 #define NV_HOST1X_NB_MLOCKS 16
 
-/* host class methods */
-enum {
-	NV_CLASS_HOST_INCR_SYNCPT = 0x0,
-	NV_CLASS_HOST_WAIT_SYNCPT = 0x8,
-	NV_CLASS_HOST_WAIT_SYNCPT_BASE = 0x9,
-	NV_CLASS_HOST_LOAD_SYNCPT_BASE = 0xb,
-	NV_CLASS_HOST_INCR_SYNCPT_BASE = 0xc,
-	NV_CLASS_HOST_INDOFF = 0x2d,
-	NV_CLASS_HOST_INDDATA = 0x2e
-};
-/*  sync point conditionals */
-enum {
-	NV_SYNCPT_IMMEDIATE = 0x0,
-	NV_SYNCPT_OP_DONE = 0x1,
-	NV_SYNCPT_RD_DONE = 0x2,
-	NV_SYNCPT_REG_WR_SAFE = 0x3,
-};
-
 static inline u32 nvhost_class_host_wait_syncpt(
 	unsigned indx, unsigned threshold)
 {
@@ -165,25 +52,30 @@ static inline u32 nvhost_class_host_wait_syncpt(
 static inline u32 nvhost_class_host_load_syncpt_base(
 	unsigned indx, unsigned threshold)
 {
-	return (indx << 24) | (threshold & 0xffffff);
+	return host1x_uclass_wait_syncpt_indx_f(indx)
+		| host1x_uclass_wait_syncpt_thresh_f(threshold);
 }
 
 static inline u32 nvhost_class_host_wait_syncpt_base(
 	unsigned indx, unsigned base_indx, unsigned offset)
 {
-	return (indx << 24) | (base_indx << 16) | offset;
+	return host1x_uclass_wait_syncpt_base_indx_f(indx)
+		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
+		| host1x_uclass_wait_syncpt_base_offset_f(offset);
 }
 
 static inline u32 nvhost_class_host_incr_syncpt_base(
 	unsigned base_indx, unsigned offset)
 {
-	return (base_indx << 24) | offset;
+	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
+		| host1x_uclass_incr_syncpt_base_offset_f(offset);
 }
 
 static inline u32 nvhost_class_host_incr_syncpt(
 	unsigned cond, unsigned indx)
 {
-	return (cond << 8) | indx;
+	return host1x_uclass_incr_syncpt_cond_f(cond)
+		| host1x_uclass_incr_syncpt_indx_f(indx);
 }
 
 enum {
@@ -195,18 +87,22 @@ enum {
 static inline u32 nvhost_class_host_indoff_reg_write(
 	unsigned mod_id, unsigned offset, bool auto_inc)
 {
-	u32 v = (0xf << 28) | (mod_id << 18) | (offset << 2);
+	u32 v = host1x_uclass_indoff_indbe_f(0xf)
+		| host1x_uclass_indoff_indmodid_f(mod_id)
+		| host1x_uclass_indoff_indroffset_f(offset);
 	if (auto_inc)
-		v |= BIT(27);
+		v |= host1x_uclass_indoff_autoinc_f(1);
 	return v;
 }
 
 static inline u32 nvhost_class_host_indoff_reg_read(
 	unsigned mod_id, unsigned offset, bool auto_inc)
 {
-	u32 v = (mod_id << 18) | (offset << 2) | 1;
+	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
+		| host1x_uclass_indoff_indroffset_f(offset)
+		| host1x_uclass_indoff_rwn_read_v();
 	if (auto_inc)
-		v |= BIT(27);
+		v |= host1x_uclass_indoff_autoinc_f(1);
 	return v;
 }
 
@@ -240,7 +136,7 @@ static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value)
 
 static inline u32 nvhost_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
 {
-	return nvhost_opcode_imm(NV_CLASS_HOST_INCR_SYNCPT,
+	return nvhost_opcode_imm(host1x_uclass_incr_syncpt_r(),
 		nvhost_class_host_incr_syncpt(cond, indx));
 }
 
diff --git a/drivers/video/tegra/host/host1x/host1x_intr.c b/drivers/video/tegra/host/host1x/host1x_intr.c
index e8d1a81c49bb..6ec6dd394ebb 100644
--- a/drivers/video/tegra/host/host1x/host1x_intr.c
+++ b/drivers/video/tegra/host/host1x/host1x_intr.c
@@ -29,6 +29,9 @@
 #include "host1x_hardware.h"
 #include "chip_support.h"
 
+/* Spacing between sync registers */
+#define REGISTER_STRIDE 4
+
 /*** HW host sync management ***/
 
 static void syncpt_thresh_mask(struct irq_data *data)
@@ -43,17 +46,23 @@ static void syncpt_thresh_unmask(struct irq_data *data)
 
 static void syncpt_thresh_cascade(unsigned int irq, struct irq_desc *desc)
 {
-	void __iomem *sync_regs = irq_desc_get_handler_data(desc);
+	struct nvhost_master *dev = irq_desc_get_handler_data(desc);
+	void __iomem *sync_regs = dev->sync_aperture;
 	unsigned long reg;
-	int id;
+	int i, id;
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 
 	chained_irq_enter(chip, desc);
 
-	reg = readl(sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
-
-	for_each_set_bit(id, &reg, 32)
-		generic_handle_irq(id + INT_SYNCPT_THRESH_BASE);
+	for (i = 0; i < dev->info.nb_pts / BITS_PER_LONG; i++) {
+		reg = readl(sync_regs +
+				host1x_sync_syncpt_thresh_cpu0_int_status_r() +
+				i * REGISTER_STRIDE);
+		for_each_set_bit(id, &reg, BITS_PER_LONG)
+			generic_handle_irq(id +
+					dev->intr.host_syncpt_irq_base +
+					i * BITS_PER_LONG);
+	}
 
 	chained_irq_exit(chip, desc);
 }
@@ -71,12 +80,12 @@ static void t20_intr_init_host_sync(struct nvhost_intr *intr)
 	int i, irq;
 
 	writel(0xffffffffUL,
-		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
+		sync_regs + host1x_sync_syncpt_thresh_int_disable_r());
 	writel(0xffffffffUL,
-		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+		sync_regs + host1x_sync_syncpt_thresh_cpu0_int_status_r());
 
-	for (i = 0; i < INT_SYNCPT_THRESH_NR; i++) {
-		irq = INT_SYNCPT_THRESH_BASE + i;
+	for (i = 0; i < dev->info.nb_pts; i++) {
+		irq = intr->host_syncpt_irq_base + i;
 		irq_set_chip_and_handler(irq, &syncpt_thresh_irq,
 			handle_simple_irq);
 		irq_set_chip_data(irq, sync_regs);
@@ -84,16 +93,16 @@ static void t20_intr_init_host_sync(struct nvhost_intr *intr)
 	}
 	irq_set_chained_handler(INT_HOST1X_MPCORE_SYNCPT,
 		syncpt_thresh_cascade);
-	irq_set_handler_data(INT_HOST1X_MPCORE_SYNCPT, sync_regs);
+	irq_set_handler_data(INT_HOST1X_MPCORE_SYNCPT, dev);
 	/* disable the ip_busy_timeout. this prevents write drops, etc.
 	 * there's no real way to recover from a hung client anyway.
 	 */
-	writel(0, sync_regs + HOST1X_SYNC_IP_BUSY_TIMEOUT);
+	writel(0, sync_regs + host1x_sync_ip_busy_timeout_r());
 
 	/* increase the auto-ack timout to the maximum value. 2d will hang
 	 * otherwise on ap20.
 	 */
-	writel(0xff, sync_regs + HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
+	writel(0xff, sync_regs + host1x_sync_ctxsw_timeout_cfg_r());
 }
 
 static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
@@ -101,7 +110,7 @@ static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
 	struct nvhost_master *dev = intr_to_dev(intr);
 	void __iomem *sync_regs = dev->sync_aperture;
 	/* write microsecond clock register */
-	writel(cpm, sync_regs + HOST1X_SYNC_USEC_CLK);
+	writel(cpm, sync_regs + host1x_sync_usec_clk_r());
 }
 
 static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
@@ -110,28 +119,39 @@ static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
 	struct nvhost_master *dev = intr_to_dev(intr);
 	void __iomem *sync_regs = dev->sync_aperture;
 	thresh &= 0xffff;
-	writel(thresh, sync_regs + (HOST1X_SYNC_SYNCPT_INT_THRESH_0 + id * 4));
+	writel(thresh, sync_regs +
+		(host1x_sync_syncpt_int_thresh_0_r() + id * REGISTER_STRIDE));
 }
 
 static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id)
 {
 	struct nvhost_master *dev = intr_to_dev(intr);
 	void __iomem *sync_regs = dev->sync_aperture;
-	writel(BIT(id),	sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0);
+
+	writel(BIT_MASK(id), sync_regs +
+			host1x_sync_syncpt_thresh_int_enable_cpu0_r() +
+			BIT_WORD(id) * REGISTER_STRIDE);
 }
 
 static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
 {
 	struct nvhost_master *dev = intr_to_dev(intr);
 	void __iomem *sync_regs = dev->sync_aperture;
-	/* disable interrupts for both cpu's */
-	writel(0, sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
-
-	/* clear status for both cpu's */
-	writel(0xffffffffu, sync_regs +
-		HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
-	writel(0xffffffffu, sync_regs +
-		HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS);
+	u32 reg;
+
+	for (reg = 0; reg <= BIT_WORD(dev->info.nb_pts) * REGISTER_STRIDE;
+			reg += REGISTER_STRIDE) {
+		/* disable interrupts for both cpu's */
+		writel(0, sync_regs +
+				host1x_sync_syncpt_thresh_int_disable_r() +
+				reg);
+
+		/* clear status for both cpu's */
+		writel(0xffffffffu, sync_regs +
+			host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg);
+		writel(0xffffffffu, sync_regs +
+			host1x_sync_syncpt_thresh_cpu1_int_status_r() + reg);
+	}
 }
 
 /**
@@ -146,10 +166,12 @@ irqreturn_t t20_intr_syncpt_thresh_isr(int irq, void *dev_id)
 
 	void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
 
-	writel(BIT(id),
-		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
-	writel(BIT(id),
-		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+	u32 reg = BIT_WORD(id) * REGISTER_STRIDE;
+
+	writel(BIT_MASK(id), sync_regs +
+		host1x_sync_syncpt_thresh_int_disable_r() + reg);
+	writel(BIT_MASK(id), sync_regs +
+		host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg);
 
 	return IRQ_WAKE_THREAD;
 }
@@ -166,21 +188,21 @@ static irqreturn_t t20_intr_host1x_isr(int irq, void *dev_id)
 	u32 ext_stat;
 	u32 addr;
 
-	stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS);
-	ext_stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
+	stat = readl(sync_regs + host1x_sync_hintstatus_r());
+	ext_stat = readl(sync_regs + host1x_sync_hintstatus_ext_r());
 
-	if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_READ_INT, ext_stat)) {
-		addr = readl(sync_regs + HOST1X_SYNC_IP_READ_TIMEOUT_ADDR);
+	if (host1x_sync_hintstatus_ext_ip_read_int_v(ext_stat)) {
+		addr = readl(sync_regs + host1x_sync_ip_read_timeout_addr_r());
 		pr_err("Host read timeout at address %x\n", addr);
 	}
 
-	if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_WRITE_INT, ext_stat)) {
-		addr = readl(sync_regs + HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR);
+	if (host1x_sync_hintstatus_ext_ip_write_int_v(ext_stat)) {
+		addr = readl(sync_regs + host1x_sync_ip_write_timeout_addr_r());
 		pr_err("Host write timeout at address %x\n", addr);
 	}
 
-	writel(ext_stat, sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
-	writel(stat, sync_regs + HOST1X_SYNC_HINTSTATUS);
+	writel(ext_stat, sync_regs + host1x_sync_hintstatus_ext_r());
+	writel(stat, sync_regs + host1x_sync_hintstatus_r());
 
 	return IRQ_HANDLED;
 }
@@ -193,11 +215,11 @@ static int t20_intr_request_host_general_irq(struct nvhost_intr *intr)
 		return 0;
 
 	/* master disable for general (not syncpt) host interrupts */
-	writel(0, sync_regs + HOST1X_SYNC_INTMASK);
+	writel(0, sync_regs + host1x_sync_intmask_r());
 
 	/* clear status & extstatus */
-	writel(0xfffffffful, sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
-	writel(0xfffffffful, sync_regs + HOST1X_SYNC_HINTSTATUS);
+	writel(0xfffffffful, sync_regs + host1x_sync_hintstatus_ext_r());
+	writel(0xfffffffful, sync_regs + host1x_sync_hintstatus_r());
 
 	err = request_irq(intr->host_general_irq, t20_intr_host1x_isr, 0,
 			"host_status", intr);
@@ -205,16 +227,16 @@ static int t20_intr_request_host_general_irq(struct nvhost_intr *intr)
 		return err;
 
 	/* enable extra interrupt sources IP_READ_INT and IP_WRITE_INT */
-	writel(BIT(30) | BIT(31), sync_regs + HOST1X_SYNC_HINTMASK_EXT);
+	writel(BIT(30) | BIT(31), sync_regs + host1x_sync_hintmask_ext_r());
 
 	/* enable extra interrupt sources */
-	writel(BIT(31), sync_regs + HOST1X_SYNC_HINTMASK);
+	writel(BIT(31), sync_regs + host1x_sync_hintmask_r());
 
 	/* enable host module interrupt to CPU0 */
-	writel(BIT(0), sync_regs + HOST1X_SYNC_INTC0MASK);
+	writel(BIT(0), sync_regs + host1x_sync_intc0mask_r());
 
 	/* master enable for general (not syncpt) host interrupts */
-	writel(BIT(0), sync_regs + HOST1X_SYNC_INTMASK);
+	writel(BIT(0), sync_regs + host1x_sync_intmask_r());
 
 	intr->host_general_irq_requested = true;
 
@@ -227,7 +249,7 @@ static void t20_intr_free_host_general_irq(struct nvhost_intr *intr)
 		void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
 
 		/* master disable for general (not syncpt) host interrupts */
-		writel(0, sync_regs + HOST1X_SYNC_INTMASK);
+		writel(0, sync_regs + host1x_sync_intmask_r());
 
 		free_irq(intr->host_general_irq, intr);
 		intr->host_general_irq_requested = false;
diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.c b/drivers/video/tegra/host/host1x/host1x_syncpt.c
index e67d2209c6ef..c53733cf2766 100644
--- a/drivers/video/tegra/host/host1x/host1x_syncpt.c
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.c
@@ -35,7 +35,7 @@ static void t20_syncpt_reset(struct nvhost_syncpt *sp, u32 id)
 {
 	struct nvhost_master *dev = syncpt_to_dev(sp);
 	int min = nvhost_syncpt_read_min(sp, id);
-	writel(min, dev->sync_aperture + (HOST1X_SYNC_SYNCPT_0 + id * 4));
+	writel(min, dev->sync_aperture + (host1x_sync_syncpt_0_r() + id * 4));
 }
 
 /**
@@ -45,7 +45,7 @@ static void t20_syncpt_reset_wait_base(struct nvhost_syncpt *sp, u32 id)
 {
 	struct nvhost_master *dev = syncpt_to_dev(sp);
 	writel(sp->base_val[id],
-		dev->sync_aperture + (HOST1X_SYNC_SYNCPT_BASE_0 + id * 4));
+		dev->sync_aperture + (host1x_sync_syncpt_base_0_r() + id * 4));
 }
 
 /**
@@ -55,7 +55,7 @@ static void t20_syncpt_read_wait_base(struct nvhost_syncpt *sp, u32 id)
 {
 	struct nvhost_master *dev = syncpt_to_dev(sp);
 	sp->base_val[id] = readl(dev->sync_aperture +
-				(HOST1X_SYNC_SYNCPT_BASE_0 + id * 4));
+				(host1x_sync_syncpt_base_0_r() + id * 4));
 }
 
 /**
@@ -70,7 +70,7 @@ static u32 t20_syncpt_update_min(struct nvhost_syncpt *sp, u32 id)
 
 	do {
 		old = nvhost_syncpt_read_min(sp, id);
-		live = readl(sync_regs + (HOST1X_SYNC_SYNCPT_0 + id * 4));
+		live = readl(sync_regs + (host1x_sync_syncpt_0_r() + id * 4));
 	} while ((u32)atomic_cmpxchg(&sp->min_val[id], old, live) != old);
 
 	if (!nvhost_syncpt_check_max(sp, id, live))
@@ -91,15 +91,19 @@ static u32 t20_syncpt_update_min(struct nvhost_syncpt *sp, u32 id)
 static void t20_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id)
 {
 	struct nvhost_master *dev = syncpt_to_dev(sp);
+	u32 reg_offset = id / 32;
+
 	BUG_ON(!nvhost_module_powered(dev->dev));
-	if (!client_managed(id) && nvhost_syncpt_min_eq_max(sp, id)) {
+	if (!nvhost_syncpt_client_managed(sp, id)
+			&& nvhost_syncpt_min_eq_max(sp, id)) {
 		dev_err(&syncpt_to_dev(sp)->dev->dev,
 			"Trying to increment syncpoint id %d beyond max\n",
 			id);
 		nvhost_debug_dump(syncpt_to_dev(sp));
 		return;
 	}
-	writel(BIT(id), dev->sync_aperture + HOST1X_SYNC_SYNCPT_CPU_INCR);
+	writel(BIT_MASK(id), dev->sync_aperture +
+			host1x_sync_syncpt_cpu_incr_r() + reg_offset * 4);
 	wmb();
 }
 
@@ -114,33 +118,16 @@ static int host1x_syncpt_patch_wait(struct nvhost_syncpt *sp,
 }
 
 
-static const char *s_syncpt_names[32] = {
-	"gfx_host",
-	"", "", "", "", "", "", "",
-	"disp0_a", "disp1_a", "avp_0",
-	"csi_vi_0", "csi_vi_1",
-	"vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
-	"2d_0", "2d_1",
-	"disp0_b", "disp1_b",
-	"3d",
-	"mpe",
-	"disp0_c", "disp1_c",
-	"vblank0", "vblank1",
-	"mpe_ebm_eof", "mpe_wr_safe",
-	"2d_tinyblt",
-	"dsi"
-};
-
-static const char *t20_syncpt_name(struct nvhost_syncpt *s, u32 id)
+static const char *t20_syncpt_name(struct nvhost_syncpt *sp, u32 id)
 {
-	BUG_ON(id >= ARRAY_SIZE(s_syncpt_names));
-	return s_syncpt_names[id];
+	struct host1x_device_info *info = &syncpt_to_dev(sp)->info;
+	return (id >= info->nb_pts) ? NULL : info->syncpt_names[id];
 }
 
 static void t20_syncpt_debug(struct nvhost_syncpt *sp)
 {
 	u32 i;
-	for (i = 0; i < NV_HOST1X_SYNCPT_NB_PTS; i++) {
+	for (i = 0; i < nvhost_syncpt_nb_pts(sp); i++) {
 		u32 max = nvhost_syncpt_read_max(sp, i);
 		u32 min = nvhost_syncpt_update_min(sp, i);
 		if (!max && !min)
@@ -152,7 +139,7 @@ static void t20_syncpt_debug(struct nvhost_syncpt *sp)
 
 	}
 
-	for (i = 0; i < NV_HOST1X_SYNCPT_NB_BASES; i++) {
+	for (i = 0; i < nvhost_syncpt_nb_bases(sp); i++) {
 		u32 base_val;
 		t20_syncpt_read_wait_base(sp, i);
 		base_val = sp->base_val[i];
@@ -170,7 +157,7 @@ static int syncpt_mutex_try_lock(struct nvhost_syncpt *sp,
 	void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
 	/* mlock registers returns 0 when the lock is aquired.
 	 * writing 0 clears the lock. */
-	return !!readl(sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+	return !!readl(sync_regs + (host1x_sync_mlock_0_r() + idx * 4));
 }
 
 static void syncpt_mutex_unlock(struct nvhost_syncpt *sp,
@@ -178,15 +165,13 @@ static void syncpt_mutex_unlock(struct nvhost_syncpt *sp,
 {
 	void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
 
-	writel(0, sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+	writel(0, sync_regs + (host1x_sync_mlock_0_r() + idx * 4));
 }
 
 int host1x_init_syncpt_support(struct nvhost_master *host,
 	struct nvhost_chip_support *op)
 {
-	host->sync_aperture = host->aperture +
-		(NV_HOST1X_CHANNEL0_BASE +
-			HOST1X_CHANNEL_SYNC_REG_BASE);
+	host->sync_aperture = host->aperture + HOST1X_CHANNEL_SYNC_REG_BASE;
 
 	op->syncpt.reset = t20_syncpt_reset;
 	op->syncpt.reset_wait_base = t20_syncpt_reset_wait_base;
@@ -199,10 +184,5 @@ int host1x_init_syncpt_support(struct nvhost_master *host,
 	op->syncpt.mutex_try_lock = syncpt_mutex_try_lock;
 	op->syncpt.mutex_unlock = syncpt_mutex_unlock;
 
-	host->syncpt.nb_pts = NV_HOST1X_SYNCPT_NB_PTS;
-	host->syncpt.nb_bases = NV_HOST1X_SYNCPT_NB_BASES;
-	host->syncpt.client_managed = NVSYNCPTS_CLIENT_MANAGED;
-	host->syncpt.nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
-
 	return 0;
 }
diff --git a/drivers/video/tegra/host/host1x/hw_host1x_channel.h b/drivers/video/tegra/host/host1x/hw_host1x_channel.h
new file mode 100644
index 000000000000..ca2f9a0778cd
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/hw_host1x_channel.h
@@ -0,0 +1,182 @@
+/*
+ * drivers/video/tegra/host/host1x/hw_host1x_channel_host1x.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_host1x_channel_host1x_h__
+#define __hw_host1x_channel_host1x_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 host1x_channel_fifostat_r(void)
+{
+	return 0x0;
+}
+static inline u32 host1x_channel_fifostat_cfempty_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_fifostat_cfempty_f(u32 v)
+{
+	return (v & 0x1) << 10;
+}
+static inline u32 host1x_channel_fifostat_cfempty_m(void)
+{
+	return 0x1 << 10;
+}
+static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
+{
+	return (r >> 10) & 0x1;
+}
+static inline u32 host1x_channel_fifostat_cfempty_notempty_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_channel_fifostat_cfempty_empty_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_fifostat_outfentries_s(void)
+{
+	return 5;
+}
+static inline u32 host1x_channel_fifostat_outfentries_f(u32 v)
+{
+	return (v & 0x1f) << 24;
+}
+static inline u32 host1x_channel_fifostat_outfentries_m(void)
+{
+	return 0x1f << 24;
+}
+static inline u32 host1x_channel_fifostat_outfentries_v(u32 r)
+{
+	return (r >> 24) & 0x1f;
+}
+static inline u32 host1x_channel_inddata_r(void)
+{
+	return 0xc;
+}
+static inline u32 host1x_channel_dmastart_r(void)
+{
+	return 0x14;
+}
+static inline u32 host1x_channel_dmaput_r(void)
+{
+	return 0x18;
+}
+static inline u32 host1x_channel_dmaget_r(void)
+{
+	return 0x1c;
+}
+static inline u32 host1x_channel_dmaend_r(void)
+{
+	return 0x20;
+}
+static inline u32 host1x_channel_dmactrl_r(void)
+{
+	return 0x24;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_run_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_channel_dmactrl_dmastop_stop_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_dmactrl_dmagetrst_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_dmactrl_dmagetrst_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 host1x_channel_dmactrl_dmagetrst_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 host1x_channel_dmactrl_dmagetrst_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 host1x_channel_dmactrl_dmainitget_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_channel_dmactrl_dmainitget_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 host1x_channel_dmactrl_dmainitget_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 host1x_channel_dmactrl_dmainitget_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+
+#endif /* __hw_host1x_channel_host1x_h__ */
diff --git a/drivers/video/tegra/host/host1x/hw_host1x_sync.h b/drivers/video/tegra/host/host1x/hw_host1x_sync.h
new file mode 100644
index 000000000000..67f0cbfb85b9
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/hw_host1x_sync.h
@@ -0,0 +1,398 @@
+/*
+ * drivers/video/tegra/host/host1x/hw_host1x_sync_host1x.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_host1x_sync_host1x_h__
+#define __hw_host1x_sync_host1x_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 host1x_sync_intmask_r(void)
+{
+	return 0x4;
+}
+static inline u32 host1x_sync_intc0mask_r(void)
+{
+	return 0x8;
+}
+static inline u32 host1x_sync_hintstatus_r(void)
+{
+	return 0x20;
+}
+static inline u32 host1x_sync_hintmask_r(void)
+{
+	return 0x24;
+}
+static inline u32 host1x_sync_hintstatus_ext_r(void)
+{
+	return 0x28;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_read_int_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_read_int_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_read_int_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_read_int_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_write_int_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_write_int_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_write_int_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 host1x_sync_hintstatus_ext_ip_write_int_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 host1x_sync_hintmask_ext_r(void)
+{
+	return 0x2c;
+}
+static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(void)
+{
+	return 0x40;
+}
+static inline u32 host1x_sync_syncpt_thresh_cpu1_int_status_r(void)
+{
+	return 0x48;
+}
+static inline u32 host1x_sync_syncpt_thresh_int_disable_r(void)
+{
+	return 0x60;
+}
+static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(void)
+{
+	return 0x68;
+}
+static inline u32 host1x_sync_cf0_setup_r(void)
+{
+	return 0x80;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_base_s(void)
+{
+	return 9;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_base_f(u32 v)
+{
+	return (v & 0x1ff) << 0;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_base_m(void)
+{
+	return 0x1ff << 0;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_base_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_limit_s(void)
+{
+	return 9;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_limit_f(u32 v)
+{
+	return (v & 0x1ff) << 16;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_limit_m(void)
+{
+	return 0x1ff << 16;
+}
+static inline u32 host1x_sync_cf0_setup_cf0_limit_v(u32 r)
+{
+	return (r >> 16) & 0x1ff;
+}
+static inline u32 host1x_sync_cmdproc_stop_r(void)
+{
+	return 0xac;
+}
+static inline u32 host1x_sync_ch_teardown_r(void)
+{
+	return 0xb0;
+}
+static inline u32 host1x_sync_usec_clk_r(void)
+{
+	return 0x1a4;
+}
+static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
+{
+	return 0x1a8;
+}
+static inline u32 host1x_sync_ip_busy_timeout_r(void)
+{
+	return 0x1bc;
+}
+static inline u32 host1x_sync_ip_read_timeout_addr_r(void)
+{
+	return 0x1c0;
+}
+static inline u32 host1x_sync_ip_write_timeout_addr_r(void)
+{
+	return 0x1c4;
+}
+static inline u32 host1x_sync_mlock_0_r(void)
+{
+	return 0x2c0;
+}
+static inline u32 host1x_sync_mlock_owner_0_r(void)
+{
+	return 0x340;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_s(void)
+{
+	return 4;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_f(u32 v)
+{
+	return (v & 0xf) << 8;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_m(void)
+{
+	return 0xf << 8;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(u32 r)
+{
+	return (r >> 8) & 0xf;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 host1x_sync_syncpt_0_r(void)
+{
+	return 0x400;
+}
+static inline u32 host1x_sync_syncpt_int_thresh_0_r(void)
+{
+	return 0x500;
+}
+static inline u32 host1x_sync_syncpt_base_0_r(void)
+{
+	return 0x600;
+}
+static inline u32 host1x_sync_syncpt_cpu_incr_r(void)
+{
+	return 0x700;
+}
+static inline u32 host1x_sync_cbread0_r(void)
+{
+	return 0x720;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_r(void)
+{
+	return 0x74c;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_s(void)
+{
+	return 9;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_f(u32 v)
+{
+	return (v & 0x1ff) << 0;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_m(void)
+{
+	return 0x1ff << 0;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_s(void)
+{
+	return 3;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_f(u32 v)
+{
+	return (v & 0x7) << 16;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_m(void)
+{
+	return 0x7 << 16;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_v(u32 r)
+{
+	return (r >> 16) & 0x7;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 host1x_sync_cfpeek_read_r(void)
+{
+	return 0x750;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_r(void)
+{
+	return 0x754;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_s(void)
+{
+	return 9;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_f(u32 v)
+{
+	return (v & 0x1ff) << 0;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_m(void)
+{
+	return 0x1ff << 0;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_s(void)
+{
+	return 9;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_f(u32 v)
+{
+	return (v & 0x1ff) << 16;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_m(void)
+{
+	return 0x1ff << 16;
+}
+static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
+{
+	return (r >> 16) & 0x1ff;
+}
+static inline u32 host1x_sync_cbstat_0_r(void)
+{
+	return 0x758;
+}
+static inline u32 host1x_sync_cbstat_0_cboffset0_s(void)
+{
+	return 16;
+}
+static inline u32 host1x_sync_cbstat_0_cboffset0_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 host1x_sync_cbstat_0_cboffset0_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 host1x_sync_cbstat_0_cboffset0_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 host1x_sync_cbstat_0_cbclass0_s(void)
+{
+	return 10;
+}
+static inline u32 host1x_sync_cbstat_0_cbclass0_f(u32 v)
+{
+	return (v & 0x3ff) << 16;
+}
+static inline u32 host1x_sync_cbstat_0_cbclass0_m(void)
+{
+	return 0x3ff << 16;
+}
+static inline u32 host1x_sync_cbstat_0_cbclass0_v(u32 r)
+{
+	return (r >> 16) & 0x3ff;
+}
+
+#endif /* __hw_host1x_sync_host1x_h__ */
diff --git a/drivers/video/tegra/host/host1x/hw_host1x_uclass.h b/drivers/video/tegra/host/host1x/hw_host1x_uclass.h
new file mode 100644
index 000000000000..ed6e4b706ab9
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/hw_host1x_uclass.h
@@ -0,0 +1,474 @@
+/*
+ * drivers/video/tegra/host/host1x/hw_host1x_uclass_host1x.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_host1x_uclass_host1x_h__
+#define __hw_host1x_uclass_host1x_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 host1x_uclass_incr_syncpt_r(void)
+{
+	return 0x0;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_v(u32 r)
+{
+	return (r >> 8) & 0xff;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_immediate_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_op_done_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_rd_done_v(void)
+{
+	return 2;
+}
+static inline u32 host1x_uclass_incr_syncpt_cond_reg_wr_safe_v(void)
+{
+	return 3;
+}
+static inline u32 host1x_uclass_incr_syncpt_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 host1x_uclass_incr_syncpt_indx_m(void)
+{
+	return 0xff << 0;
+}
+static inline u32 host1x_uclass_incr_syncpt_indx_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 host1x_uclass_wait_syncpt_r(void)
+{
+	return 0x8;
+}
+static inline u32 host1x_uclass_wait_syncpt_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 host1x_uclass_wait_syncpt_indx_m(void)
+{
+	return 0xff << 24;
+}
+static inline u32 host1x_uclass_wait_syncpt_indx_v(u32 r)
+{
+	return (r >> 24) & 0xff;
+}
+static inline u32 host1x_uclass_wait_syncpt_thresh_s(void)
+{
+	return 24;
+}
+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 host1x_uclass_wait_syncpt_thresh_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 host1x_uclass_wait_syncpt_thresh_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_r(void)
+{
+	return 0x9;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_indx_m(void)
+{
+	return 0xff << 24;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_indx_v(u32 r)
+{
+	return (r >> 24) & 0xff;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 16;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_m(void)
+{
+	return 0xff << 16;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_offset_s(void)
+{
+	return 16;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_offset_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 host1x_uclass_wait_syncpt_base_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 host1x_uclass_load_syncpt_base_r(void)
+{
+	return 0xb;
+}
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_m(void)
+{
+	return 0xff << 24;
+}
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_v(u32 r)
+{
+	return (r >> 24) & 0xff;
+}
+static inline u32 host1x_uclass_load_syncpt_base_value_s(void)
+{
+	return 24;
+}
+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 host1x_uclass_load_syncpt_base_value_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 host1x_uclass_load_syncpt_base_value_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_r(void)
+{
+	return 0xc;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_m(void)
+{
+	return 0xff << 24;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_v(u32 r)
+{
+	return (r >> 24) & 0xff;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_offset_s(void)
+{
+	return 24;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_offset_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 host1x_uclass_incr_syncpt_base_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 host1x_uclass_indoff_r(void)
+{
+	return 0x2d;
+}
+static inline u32 host1x_uclass_indoff_indbe_s(void)
+{
+	return 4;
+}
+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
+{
+	return (v & 0xf) << 28;
+}
+static inline u32 host1x_uclass_indoff_indbe_m(void)
+{
+	return 0xf << 28;
+}
+static inline u32 host1x_uclass_indoff_indbe_v(u32 r)
+{
+	return (r >> 28) & 0xf;
+}
+static inline u32 host1x_uclass_indoff_autoinc_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
+{
+	return (v & 0x1) << 27;
+}
+static inline u32 host1x_uclass_indoff_autoinc_m(void)
+{
+	return 0x1 << 27;
+}
+static inline u32 host1x_uclass_indoff_autoinc_v(u32 r)
+{
+	return (r >> 27) & 0x1;
+}
+static inline u32 host1x_uclass_indoff_spool_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_spool_f(u32 v)
+{
+	return (v & 0x1) << 26;
+}
+static inline u32 host1x_uclass_indoff_spool_m(void)
+{
+	return 0x1 << 26;
+}
+static inline u32 host1x_uclass_indoff_spool_v(u32 r)
+{
+	return (r >> 26) & 0x1;
+}
+static inline u32 host1x_uclass_indoff_indoffset_s(void)
+{
+	return 24;
+}
+static inline u32 host1x_uclass_indoff_indoffset_f(u32 v)
+{
+	return (v & 0xffffff) << 2;
+}
+static inline u32 host1x_uclass_indoff_indoffset_m(void)
+{
+	return 0xffffff << 2;
+}
+static inline u32 host1x_uclass_indoff_indoffset_v(u32 r)
+{
+	return (r >> 2) & 0xffffff;
+}
+static inline u32 host1x_uclass_indoff_indmodid_s(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+static inline u32 host1x_uclass_indoff_indmodid_m(void)
+{
+	return 0xff << 18;
+}
+static inline u32 host1x_uclass_indoff_indmodid_v(u32 r)
+{
+	return (r >> 18) & 0xff;
+}
+static inline u32 host1x_uclass_indoff_indmodid_host1x_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_uclass_indoff_indmodid_mpe_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_indmodid_vi_v(void)
+{
+	return 2;
+}
+static inline u32 host1x_uclass_indoff_indmodid_epp_v(void)
+{
+	return 3;
+}
+static inline u32 host1x_uclass_indoff_indmodid_isp_v(void)
+{
+	return 4;
+}
+static inline u32 host1x_uclass_indoff_indmodid_gr2d_v(void)
+{
+	return 5;
+}
+static inline u32 host1x_uclass_indoff_indmodid_gr3d_v(void)
+{
+	return 6;
+}
+static inline u32 host1x_uclass_indoff_indmodid_display_v(void)
+{
+	return 8;
+}
+static inline u32 host1x_uclass_indoff_indmodid_tvo_v(void)
+{
+	return 11;
+}
+static inline u32 host1x_uclass_indoff_indmodid_displayb_v(void)
+{
+	return 9;
+}
+static inline u32 host1x_uclass_indoff_indmodid_dsi_v(void)
+{
+	return 12;
+}
+static inline u32 host1x_uclass_indoff_indmodid_hdmi_v(void)
+{
+	return 10;
+}
+static inline u32 host1x_uclass_indoff_indmodid_dsib_v(void)
+{
+	return 16;
+}
+static inline u32 host1x_uclass_indoff_indroffset_s(void)
+{
+	return 16;
+}
+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
+{
+	return (v & 0xffff) << 2;
+}
+static inline u32 host1x_uclass_indoff_indroffset_m(void)
+{
+	return 0xffff << 2;
+}
+static inline u32 host1x_uclass_indoff_indroffset_v(u32 r)
+{
+	return (r >> 2) & 0xffff;
+}
+static inline u32 host1x_uclass_indoff_acctype_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_acctype_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 host1x_uclass_indoff_acctype_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 host1x_uclass_indoff_acctype_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 host1x_uclass_indoff_acctype_reg_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_uclass_indoff_acctype_fb_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_rwn_s(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_indoff_rwn_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 host1x_uclass_indoff_rwn_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 host1x_uclass_indoff_rwn_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 host1x_uclass_indoff_rwn_write_v(void)
+{
+	return 0;
+}
+static inline u32 host1x_uclass_indoff_rwn_read_v(void)
+{
+	return 1;
+}
+static inline u32 host1x_uclass_inddata_r(void)
+{
+	return 0x2e;
+}
+
+#endif /* __hw_host1x_uclass_host1x_h__ */
diff --git a/drivers/video/tegra/host/mpe/mpe.c b/drivers/video/tegra/host/mpe/mpe.c
index cee0714bf079..57770ce617d7 100644
--- a/drivers/video/tegra/host/mpe/mpe.c
+++ b/drivers/video/tegra/host/mpe/mpe.c
@@ -140,7 +140,7 @@ static void restore_begin(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* set class to host */
 	ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+					host1x_uclass_incr_syncpt_base_r(), 1);
 	/* increment sync point base */
 	ptr[1] = nvhost_class_host_incr_syncpt_base(h->waitbase, 1);
 	/* set class to MPE */
@@ -159,7 +159,8 @@ static void restore_ram(u32 *ptr, unsigned words,
 static void restore_end(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* syncpt increment to track restore gather. */
-	ptr[0] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+	ptr[0] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(),
 			h->syncpt);
 }
 #define RESTORE_END_SIZE 1
@@ -217,23 +218,26 @@ static void __init save_begin(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* MPE: when done, increment syncpt to base+1 */
 	ptr[0] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID, 0, 0);
-	ptr[1] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, h->syncpt);
+	ptr[1] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(), h->syncpt);
 	/* host: wait for syncpt base+1 */
 	ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+					host1x_uclass_wait_syncpt_base_r(), 1);
 	ptr[3] = nvhost_class_host_wait_syncpt_base(h->syncpt, h->waitbase, 1);
 	/* host: signal context read thread to start reading */
-	ptr[4] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE, h->syncpt);
+	ptr[4] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_immediate_v(),
+			h->syncpt);
 }
 #define SAVE_BEGIN_SIZE 5
 
 static void __init save_direct(u32 *ptr, u32 start_reg, u32 count)
 {
 	ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INDOFF, 1);
+					host1x_uclass_indoff_r(), 1);
 	ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_MPE,
 						start_reg, true);
-	ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+	ptr[2] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 #define SAVE_DIRECT_SIZE 3
 
@@ -248,10 +252,10 @@ static void __init save_set_ram_cmd(u32 *ptr, u32 cmd_reg, u32 count)
 static void __init save_read_ram_data_nasty(u32 *ptr, u32 data_reg)
 {
 	ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_INDOFF, 1);
+					host1x_uclass_indoff_r(), 1);
 	ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_MPE,
 						data_reg, false);
-	ptr[2] = nvhost_opcode_imm(NV_CLASS_HOST_INDDATA, 0);
+	ptr[2] = nvhost_opcode_imm(host1x_uclass_inddata_r(), 0);
 	/* write junk data to avoid 'cached problem with register memory' */
 	ptr[3] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID,
 					data_reg, 1);
@@ -263,10 +267,10 @@ static void __init save_end(struct host1x_hwctx_handler *h, u32 *ptr)
 {
 	/* Wait for context read service to finish (cpu incr 3) */
 	ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-					NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+					host1x_uclass_wait_syncpt_base_r(), 1);
 	ptr[1] = nvhost_class_host_wait_syncpt_base(h->syncpt, h->waitbase, 3);
 	/* Advance syncpoint base */
-	ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+	ptr[2] = nvhost_opcode_nonincr(host1x_uclass_incr_syncpt_base_r(), 1);
 	ptr[3] = nvhost_class_host_incr_syncpt_base(h->waitbase, 3);
 	/* set class back to the unit */
 	ptr[4] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID, 0, 0);
@@ -579,7 +583,13 @@ struct nvhost_hwctx_handler *nvhost_mpe_ctxhandler_init(u32 syncpt,
 
 int nvhost_mpe_prepare_power_off(struct nvhost_device *dev)
 {
-	return host1x_save_context(dev, NVSYNCPT_MPE);
+	struct nvhost_hwctx *cur_ctx = dev->channel->cur_ctx;
+	int err = 0;
+	if (cur_ctx)
+		err = host1x_save_context(dev,
+			to_host1x_hwctx_handler(cur_ctx->h)->syncpt);
+
+	return err;
 }
 
 enum mpe_ip_ver {
diff --git a/drivers/video/tegra/host/nvhost_cdma.c b/drivers/video/tegra/host/nvhost_cdma.c
index 409d4dd6ecf2..dae3b7e6182d 100644
--- a/drivers/video/tegra/host/nvhost_cdma.c
+++ b/drivers/video/tegra/host/nvhost_cdma.c
@@ -242,7 +242,7 @@ static void update_cdma_locked(struct nvhost_cdma *cdma)
 }
 
 void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
-		struct nvhost_syncpt *syncpt, struct device *dev)
+		struct nvhost_syncpt *syncpt, struct nvhost_device *dev)
 {
 	u32 get_restart;
 	u32 syncpt_incrs;
@@ -251,7 +251,7 @@ void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
 
 	syncpt_val = nvhost_syncpt_update_min(syncpt, cdma->timeout.syncpt_id);
 
-	dev_dbg(dev,
+	dev_dbg(&dev->dev,
 		"%s: starting cleanup (thresh %d)\n",
 		__func__, syncpt_val);
 
@@ -262,7 +262,7 @@ void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
 	 * where a syncpt incr happens just prior/during the teardown.
 	 */
 
-	dev_dbg(dev,
+	dev_dbg(&dev->dev,
 		"%s: skip completed buffers still in sync_queue\n",
 		__func__);
 
@@ -270,7 +270,7 @@ void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
 		if (syncpt_val < job->syncpt_end)
 			break;
 
-		nvhost_job_dump(dev, job);
+		nvhost_job_dump(&dev->dev, job);
 	}
 
 	/*
@@ -288,7 +288,7 @@ void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
 	 * properly for this buffer and resources are freed.
 	 */
 
-	dev_dbg(dev,
+	dev_dbg(&dev->dev,
 		"%s: perform CPU incr on pending same ctx buffers\n",
 		__func__);
 
@@ -306,22 +306,23 @@ void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
 		job->timeout = 0;
 
 		syncpt_incrs = job->syncpt_end - syncpt_val;
-		dev_dbg(dev,
+		dev_dbg(&dev->dev,
 			"%s: CPU incr (%d)\n", __func__, syncpt_incrs);
 
-		nvhost_job_dump(dev, job);
+		nvhost_job_dump(&dev->dev, job);
 
 		/* safe to use CPU to incr syncpts */
 		cdma_op().timeout_cpu_incr(cdma,
 				job->first_get,
 				syncpt_incrs,
 				job->syncpt_end,
-				job->num_slots);
+				job->num_slots,
+				dev->waitbases);
 
 		syncpt_val += syncpt_incrs;
 	}
 
-	dev_dbg(dev,
+	dev_dbg(&dev->dev,
 		"%s: finished sync_queue modification\n", __func__);
 
 	/* roll back DMAGET and start up channel again */
diff --git a/drivers/video/tegra/host/nvhost_cdma.h b/drivers/video/tegra/host/nvhost_cdma.h
index e4a19e6ab113..a9522c5f6326 100644
--- a/drivers/video/tegra/host/nvhost_cdma.h
+++ b/drivers/video/tegra/host/nvhost_cdma.h
@@ -113,5 +113,5 @@ void	nvhost_cdma_peek(struct nvhost_cdma *cdma,
 unsigned int nvhost_cdma_wait_locked(struct nvhost_cdma *cdma,
 		enum cdma_event event);
 void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
-		struct nvhost_syncpt *syncpt, struct device *dev);
+		struct nvhost_syncpt *syncpt, struct nvhost_device *dev);
 #endif
diff --git a/drivers/video/tegra/host/nvhost_intr.c b/drivers/video/tegra/host/nvhost_intr.c
index d61602c4e94e..38a04f151e87 100644
--- a/drivers/video/tegra/host/nvhost_intr.c
+++ b/drivers/video/tegra/host/nvhost_intr.c
@@ -282,7 +282,6 @@ int nvhost_intr_add_action(struct nvhost_intr *intr, u32 id, u32 thresh,
 	waiter->data = data;
 	waiter->count = 1;
 
-	BUG_ON(id >= intr_to_dev(intr)->syncpt.nb_pts);
 	syncpt = intr->syncpt + id;
 
 	spin_lock(&syncpt->lock);
@@ -346,11 +345,11 @@ int nvhost_intr_init(struct nvhost_intr *intr, u32 irq_gen, u32 irq_sync)
 {
 	unsigned int id;
 	struct nvhost_intr_syncpt *syncpt;
-	struct nvhost_master *host =
-		container_of(intr, struct nvhost_master, intr);
-	u32 nb_pts = host->syncpt.nb_pts;
+	struct nvhost_master *host = intr_to_dev(intr);
+	u32 nb_pts = nvhost_syncpt_nb_pts(&host->syncpt);
 
 	mutex_init(&intr->mutex);
+	intr->host_syncpt_irq_base = irq_sync;
 	intr_op().init_host_sync(intr);
 	intr->host_general_irq = irq_gen;
 	intr->host_general_irq_requested = false;
@@ -399,7 +398,7 @@ void nvhost_intr_stop(struct nvhost_intr *intr)
 {
 	unsigned int id;
 	struct nvhost_intr_syncpt *syncpt;
-	u32 nb_pts = intr_to_dev(intr)->syncpt.nb_pts;
+	u32 nb_pts = nvhost_syncpt_nb_pts(&intr_to_dev(intr)->syncpt);
 
 	BUG_ON(!(intr_op().disable_all_syncpt_intrs &&
 		 intr_op().free_host_general_irq));
diff --git a/drivers/video/tegra/host/nvhost_intr.h b/drivers/video/tegra/host/nvhost_intr.h
index eea9d837998f..cf0b6b9e8934 100644
--- a/drivers/video/tegra/host/nvhost_intr.h
+++ b/drivers/video/tegra/host/nvhost_intr.h
@@ -71,6 +71,7 @@ struct nvhost_intr {
 	struct nvhost_intr_syncpt *syncpt;
 	struct mutex mutex;
 	int host_general_irq;
+	int host_syncpt_irq_base;
 	bool host_general_irq_requested;
 };
 #define intr_to_dev(x) container_of(x, struct nvhost_master, intr)
diff --git a/drivers/video/tegra/host/nvhost_syncpt.c b/drivers/video/tegra/host/nvhost_syncpt.c
index 34f7a0b08315..06f535207876 100644
--- a/drivers/video/tegra/host/nvhost_syncpt.c
+++ b/drivers/video/tegra/host/nvhost_syncpt.c
@@ -40,9 +40,9 @@ void nvhost_syncpt_reset(struct nvhost_syncpt *sp)
 	u32 i;
 	BUG_ON(!(syncpt_op().reset && syncpt_op().reset_wait_base));
 
-	for (i = 0; i < sp->nb_pts; i++)
+	for (i = 0; i < nvhost_syncpt_nb_pts(sp); i++)
 		syncpt_op().reset(sp, i);
-	for (i = 0; i < sp->nb_bases; i++)
+	for (i = 0; i < nvhost_syncpt_nb_bases(sp); i++)
 		syncpt_op().reset_wait_base(sp, i);
 	wmb();
 }
@@ -55,14 +55,14 @@ void nvhost_syncpt_save(struct nvhost_syncpt *sp)
 	u32 i;
 	BUG_ON(!(syncpt_op().update_min && syncpt_op().read_wait_base));
 
-	for (i = 0; i < sp->nb_pts; i++) {
-		if (client_managed(i))
+	for (i = 0; i < nvhost_syncpt_nb_pts(sp); i++) {
+		if (nvhost_syncpt_client_managed(sp, i))
 			syncpt_op().update_min(sp, i);
 		else
 			BUG_ON(!nvhost_syncpt_min_eq_max(sp, i));
 	}
 
-	for (i = 0; i < sp->nb_bases; i++)
+	for (i = 0; i < nvhost_syncpt_nb_bases(sp); i++)
 		syncpt_op().read_wait_base(sp, i);
 }
 
@@ -123,7 +123,7 @@ void nvhost_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id)
  */
 void nvhost_syncpt_incr(struct nvhost_syncpt *sp, u32 id)
 {
-	if (client_managed(id))
+	if (nvhost_syncpt_client_managed(sp, id))
 		nvhost_syncpt_incr_max(sp, id, 1);
 	nvhost_module_busy(syncpt_to_dev(sp)->dev);
 	nvhost_syncpt_cpu_incr(sp, id);
@@ -298,7 +298,7 @@ bool nvhost_syncpt_is_expired(
 	 * If future valueis zero, we have a client managed sync point. In that
 	 * case we do a direct comparison.
 	 */
-	if (!client_managed(id))
+	if (!nvhost_syncpt_client_managed(sp, id))
 		return future_val - thresh >= current_val - thresh;
 	else
 		return (s32)(current_val - thresh) >= 0;
@@ -368,10 +368,15 @@ int nvhost_syncpt_init(struct nvhost_device *dev,
 	int err = 0;
 
 	/* Allocate structs for min, max and base values */
-	sp->min_val = kzalloc(sizeof(atomic_t) * sp->nb_pts, GFP_KERNEL);
-	sp->max_val = kzalloc(sizeof(atomic_t) * sp->nb_pts, GFP_KERNEL);
-	sp->base_val = kzalloc(sizeof(u32) * sp->nb_bases, GFP_KERNEL);
-	sp->lock_counts = kzalloc(sizeof(atomic_t) * sp->nb_mlocks, GFP_KERNEL);
+	sp->min_val = kzalloc(sizeof(atomic_t) * nvhost_syncpt_nb_pts(sp),
+			GFP_KERNEL);
+	sp->max_val = kzalloc(sizeof(atomic_t) * nvhost_syncpt_nb_pts(sp),
+			GFP_KERNEL);
+	sp->base_val = kzalloc(sizeof(u32) * nvhost_syncpt_nb_bases(sp),
+			GFP_KERNEL);
+	sp->lock_counts =
+		kzalloc(sizeof(atomic_t) * nvhost_syncpt_nb_mlocks(sp),
+			GFP_KERNEL);
 
 	if (!(sp->min_val && sp->max_val && sp->base_val && sp->lock_counts)) {
 		/* frees happen in the deinit */
@@ -386,15 +391,15 @@ int nvhost_syncpt_init(struct nvhost_device *dev,
 	}
 
 	/* Allocate two attributes for each sync point: min and max */
-	sp->syncpt_attrs = kzalloc(sizeof(*sp->syncpt_attrs) * sp->nb_pts * 2,
-			GFP_KERNEL);
+	sp->syncpt_attrs = kzalloc(sizeof(*sp->syncpt_attrs)
+			* nvhost_syncpt_nb_pts(sp) * 2, GFP_KERNEL);
 	if (!sp->syncpt_attrs) {
 		err = -ENOMEM;
 		goto fail;
 	}
 
 	/* Fill in the attributes */
-	for (i = 0; i < sp->nb_pts; i++) {
+	for (i = 0; i < nvhost_syncpt_nb_pts(sp); i++) {
 		char name[MAX_SYNCPT_LENGTH];
 		struct kobject *kobj;
 		struct nvhost_syncpt_attr *min = &sp->syncpt_attrs[i*2];
@@ -455,3 +460,23 @@ void nvhost_syncpt_deinit(struct nvhost_syncpt *sp)
 	kfree(sp->syncpt_attrs);
 	sp->syncpt_attrs = NULL;
 }
+
+int nvhost_syncpt_client_managed(struct nvhost_syncpt *sp, u32 id)
+{
+	return BIT(id) & syncpt_to_dev(sp)->info.client_managed;
+}
+
+int nvhost_syncpt_nb_pts(struct nvhost_syncpt *sp)
+{
+	return syncpt_to_dev(sp)->info.nb_pts;
+}
+
+int nvhost_syncpt_nb_bases(struct nvhost_syncpt *sp)
+{
+	return syncpt_to_dev(sp)->info.nb_bases;
+}
+
+int nvhost_syncpt_nb_mlocks(struct nvhost_syncpt *sp)
+{
+	return syncpt_to_dev(sp)->info.nb_mlocks;
+}
diff --git a/drivers/video/tegra/host/nvhost_syncpt.h b/drivers/video/tegra/host/nvhost_syncpt.h
index e39d3c3d8887..04402fb6ac51 100644
--- a/drivers/video/tegra/host/nvhost_syncpt.h
+++ b/drivers/video/tegra/host/nvhost_syncpt.h
@@ -42,18 +42,14 @@ struct nvhost_syncpt {
 	atomic_t *min_val;
 	atomic_t *max_val;
 	u32 *base_val;
-	u32 nb_pts;
-	u32 nb_bases;
-	u32 client_managed;
 	atomic_t *lock_counts;
-	u32 nb_mlocks;
+	const char **syncpt_names;
 	struct nvhost_syncpt_attr *syncpt_attrs;
 };
 
 int nvhost_syncpt_init(struct nvhost_device *, struct nvhost_syncpt *);
 void nvhost_syncpt_deinit(struct nvhost_syncpt *);
 
-#define client_managed(id) (BIT(id) & sp->client_managed)
 #define syncpt_to_dev(sp) container_of(sp, struct nvhost_master, syncpt)
 #define SYNCPT_CHECK_PERIOD (2 * HZ)
 #define MAX_STUCK_CHECK_COUNT 15
@@ -90,11 +86,16 @@ static inline u32 nvhost_syncpt_read_min(struct nvhost_syncpt *sp, u32 id)
 	return (u32)atomic_read(&sp->min_val[id]);
 }
 
+int nvhost_syncpt_client_managed(struct nvhost_syncpt *sp, u32 id);
+int nvhost_syncpt_nb_pts(struct nvhost_syncpt *sp);
+int nvhost_syncpt_nb_bases(struct nvhost_syncpt *sp);
+int nvhost_syncpt_nb_mlocks(struct nvhost_syncpt *sp);
+
 static inline bool nvhost_syncpt_check_max(struct nvhost_syncpt *sp,
 		u32 id, u32 real)
 {
 	u32 max;
-	if (client_managed(id))
+	if (nvhost_syncpt_client_managed(sp, id))
 		return true;
 	max = nvhost_syncpt_read_max(sp, id);
 	return (s32)(max - real) >= 0;
@@ -141,7 +142,7 @@ void nvhost_syncpt_debug(struct nvhost_syncpt *sp);
 
 static inline int nvhost_syncpt_is_valid(struct nvhost_syncpt *sp, u32 id)
 {
-	return id != NVSYNCPT_INVALID && id < sp->nb_pts;
+	return id != NVSYNCPT_INVALID && id < nvhost_syncpt_nb_pts(sp);
 }
 
 int nvhost_mutex_try_lock(struct nvhost_syncpt *sp, int idx);
diff --git a/drivers/video/tegra/host/t20/t20.c b/drivers/video/tegra/host/t20/t20.c
index 9c6e87a98f13..9b27c74ffd48 100644
--- a/drivers/video/tegra/host/t20/t20.c
+++ b/drivers/video/tegra/host/t20/t20.c
@@ -47,10 +47,62 @@
 #define NVMODMUTEX_VI		(8)
 #define NVMODMUTEX_DSI		(9)
 
-#define T20_NVHOST_NUMCHANNELS	(NV_HOST1X_CHANNELS - 1)
-
 static int t20_num_alloc_channels = 0;
 
+static struct resource tegra_host1x01_resources[] = {
+	{
+		.start = TEGRA_HOST1X_BASE,
+		.end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = INT_SYNCPT_THRESH_BASE,
+		.end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = INT_HOST1X_MPCORE_GENERAL,
+		.end = INT_HOST1X_MPCORE_GENERAL,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static const char *s_syncpt_names[32] = {
+	"gfx_host",
+	"", "", "", "", "", "", "",
+	"disp0_a", "disp1_a", "avp_0",
+	"csi_vi_0", "csi_vi_1",
+	"vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
+	"2d_0", "2d_1",
+	"disp0_b", "disp1_b",
+	"3d",
+	"mpe",
+	"disp0_c", "disp1_c",
+	"vblank0", "vblank1",
+	"mpe_ebm_eof", "mpe_wr_safe",
+	"2d_tinyblt",
+	"dsi"
+};
+
+static struct host1x_device_info host1x01_info = {
+	.nb_channels	= 8,
+	.nb_pts		= 32,
+	.nb_mlocks	= 16,
+	.nb_bases	= 8,
+	.syncpt_names	= s_syncpt_names,
+	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device tegra_host1x01_device = {
+	.dev		= {.platform_data = &host1x01_info},
+	.name		= "host1x",
+	.id		= -1,
+	.resource	= tegra_host1x01_resources,
+	.num_resources	= ARRAY_SIZE(tegra_host1x01_resources),
+	.clocks		= {{"host1x", UINT_MAX}, {} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+};
+
 static struct nvhost_device tegra_display01_device = {
 	.name		= "display",
 	.id		= -1,
@@ -199,7 +251,6 @@ int tegra2_register_host1x_devices(void)
 
 static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
 {
-	p += NV_HOST1X_CHANNEL0_BASE;
 	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
 	return p;
 }
@@ -250,10 +301,12 @@ static void t20_free_nvhost_channel(struct nvhost_channel *ch)
 	nvhost_free_channel_internal(ch, &t20_num_alloc_channels);
 }
 
-static struct nvhost_channel *t20_alloc_nvhost_channel(int chindex)
+static struct nvhost_channel *t20_alloc_nvhost_channel(
+		struct nvhost_device *dev)
 {
-	return nvhost_alloc_channel_internal(chindex,
-		T20_NVHOST_NUMCHANNELS, &t20_num_alloc_channels);
+	return nvhost_alloc_channel_internal(dev->index,
+		nvhost_get_host(dev)->info.nb_channels,
+		&t20_num_alloc_channels);
 }
 
 int nvhost_init_t20_support(struct nvhost_master *host,
diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c
index acd5d928b1a1..9f43036c8523 100644
--- a/drivers/video/tegra/host/t30/t30.c
+++ b/drivers/video/tegra/host/t30/t30.c
@@ -47,10 +47,62 @@
 #define NVMODMUTEX_VI		(8)
 #define NVMODMUTEX_DSI		(9)
 
-#define T30_NVHOST_NUMCHANNELS	(NV_HOST1X_CHANNELS - 1)
-
 static int t30_num_alloc_channels = 0;
 
+static struct resource tegra_host1x01_resources[] = {
+	{
+		.start = TEGRA_HOST1X_BASE,
+		.end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = INT_SYNCPT_THRESH_BASE,
+		.end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = INT_HOST1X_MPCORE_GENERAL,
+		.end = INT_HOST1X_MPCORE_GENERAL,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static const char *s_syncpt_names[32] = {
+	"gfx_host",
+	"", "", "", "", "", "", "",
+	"disp0_a", "disp1_a", "avp_0",
+	"csi_vi_0", "csi_vi_1",
+	"vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
+	"2d_0", "2d_1",
+	"disp0_b", "disp1_b",
+	"3d",
+	"mpe",
+	"disp0_c", "disp1_c",
+	"vblank0", "vblank1",
+	"mpe_ebm_eof", "mpe_wr_safe",
+	"2d_tinyblt",
+	"dsi"
+};
+
+static struct host1x_device_info host1x01_info = {
+	.nb_channels	= 8,
+	.nb_pts		= 32,
+	.nb_mlocks	= 16,
+	.nb_bases	= 8,
+	.syncpt_names	= s_syncpt_names,
+	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device tegra_host1x01_device = {
+	.dev		= {.platform_data = &host1x01_info},
+	.name		= "host1x",
+	.id		= -1,
+	.resource	= tegra_host1x01_resources,
+	.num_resources	= ARRAY_SIZE(tegra_host1x01_resources),
+	.clocks		= {{"host1x", UINT_MAX}, {} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+};
+
 static struct nvhost_device tegra_display01_device = {
 	.name		= "display",
 	.id		= -1,
@@ -226,7 +278,6 @@ static inline int t30_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
 
 static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx)
 {
-	p += NV_HOST1X_CHANNEL0_BASE;
 	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
 	return p;
 }
@@ -265,10 +316,12 @@ static void t30_free_nvhost_channel(struct nvhost_channel *ch)
 	nvhost_free_channel_internal(ch, &t30_num_alloc_channels);
 }
 
-static struct nvhost_channel *t30_alloc_nvhost_channel(int chindex)
+static struct nvhost_channel *t30_alloc_nvhost_channel(
+		struct nvhost_device *dev)
 {
-	return nvhost_alloc_channel_internal(chindex,
-		T30_NVHOST_NUMCHANNELS, &t30_num_alloc_channels);
+	return nvhost_alloc_channel_internal(dev->index,
+		nvhost_get_host(dev)->info.nb_channels,
+		&t30_num_alloc_channels);
 }
 
 int nvhost_init_t30_support(struct nvhost_master *host,