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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-12-18 05:32:28 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-12-18 05:32:28 +0100
commit18d5f4a85d71d7921e9b121aeefb9c12c888d781 (patch)
tree9d4db4ca68a4aefea6007cf02223aa24630dada2 /drivers/video/tegra
parent45c163d2da4d3fae3f555bd91d68d6043d2c1f7b (diff)
video: tegra: fb: fix pixel clock polarity
The pixel clock polarity setting was wrong: The kernel display flags are rather somewhat confusing: The flags specify the edge where the data should be driven by the controller (and hence not sampled by the display!). Please note that we don't change the default pixel clock polarity.
Diffstat (limited to 'drivers/video/tegra')
-rw-r--r--drivers/video/tegra/fb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/tegra/fb.c b/drivers/video/tegra/fb.c
index b7aa066751fc..9d6f15cda48b 100644
--- a/drivers/video/tegra/fb.c
+++ b/drivers/video/tegra/fb.c
@@ -610,10 +610,10 @@ static int parse_opt(struct tegra_dc_out *out, char *this_opt)
} else if (!strncmp(this_opt, "pixclockpol:", 12)) {
if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
out->out_pins[TEGRA_DC_OUT_PIN_PIXEL_CLOCK].pol =
- TEGRA_DC_OUT_PIN_POL_LOW;
+ TEGRA_DC_OUT_PIN_POL_HIGH;
} else {
out->out_pins[TEGRA_DC_OUT_PIN_PIXEL_CLOCK].pol =
- TEGRA_DC_OUT_PIN_POL_HIGH;
+ TEGRA_DC_OUT_PIN_POL_LOW;
}
return 0;
}