video: tegra: host: Move host1x code into own directory

Move source files related to host1x into an own directory.

Bug 871237

Change-Id: I6fa3ef057f8b788c37dd2ab698271cf7508711c6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/71783
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

24 files changed, 613 insertions, 622 deletions

diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h
index 0f9a0531a77e..994edfe46d31 100644
--- a/drivers/video/tegra/dc/dc_priv.h
+++ b/drivers/video/tegra/dc/dc_priv.h
@@ -27,7 +27,7 @@
 #include <mach/dc.h>
 
 #include "../host/dev.h"
-#include "../host/t20/syncpt_t20.h"
+#include "../host/host1x/host1x_syncpt.h"
 
 #include <mach/tegra_dc_ext.h>
 
diff --git a/drivers/video/tegra/host/Makefile b/drivers/video/tegra/host/Makefile
index bc3d2fa08210..4fd19ac809b8 100644
--- a/drivers/video/tegra/host/Makefile
+++ b/drivers/video/tegra/host/Makefile
@@ -13,6 +13,7 @@ nvhost-objs = \
 
 obj-$(CONFIG_TEGRA_GRHOST) += mpe/
 obj-$(CONFIG_TEGRA_GRHOST) += gr3d/
+obj-$(CONFIG_TEGRA_GRHOST) += host1x/
 obj-$(CONFIG_TEGRA_GRHOST) += t20/
 obj-$(CONFIG_TEGRA_GRHOST) += t30/
 obj-$(CONFIG_TEGRA_GRHOST) += nvhost.o
diff --git a/drivers/video/tegra/host/gr3d/gr3d.c b/drivers/video/tegra/host/gr3d/gr3d.c
index 680fd13bbc33..f7f892b883a0 100644
--- a/drivers/video/tegra/host/gr3d/gr3d.c
+++ b/drivers/video/tegra/host/gr3d/gr3d.c
@@ -25,8 +25,9 @@
 #include <mach/nvmap.h>
 #include <linux/slab.h>
 #include "t20/t20.h"
-#include "t20/hardware_t20.h"
-#include "t20/syncpt_t20.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
 #include "nvhost_hwctx.h"
 #include "dev.h"
 #include "gr3d.h"
@@ -149,5 +150,5 @@ void nvhost_3dctx_put(struct nvhost_hwctx *ctx)
 
 int nvhost_gr3d_prepare_power_off(struct nvhost_module *mod)
 {
-	return nvhost_t20_save_context(mod, NVSYNCPT_3D);
+	return host1x_save_context(mod, NVSYNCPT_3D);
 }
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.c b/drivers/video/tegra/host/gr3d/gr3d_t20.c
index d66be77446fd..c1b25bd164c3 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t20.c
+++ b/drivers/video/tegra/host/gr3d/gr3d_t20.c
@@ -22,9 +22,9 @@
 
 #include "nvhost_hwctx.h"
 #include "dev.h"
-#include "t20/channel_t20.h"
-#include "t20/hardware_t20.h"
-#include "t20/syncpt_t20.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
 #include "gr3d.h"
 
 #include <linux/slab.h>
@@ -215,7 +215,7 @@ static u32 *save_regs_v0(u32 *ptr, unsigned int *pending,
 			ptr += RESTORE_INDIRECT_SIZE;
 			break;
 		}
-		drain_result = nvhost_drain_read_fifo(chan_regs,
+		drain_result = host1x_drain_read_fifo(chan_regs,
 			ptr, count, pending);
 		BUG_ON(drain_result < 0);
 		ptr += count;
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.c b/drivers/video/tegra/host/gr3d/gr3d_t30.c
index e78d5930d031..5f991a41db85 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t30.c
+++ b/drivers/video/tegra/host/gr3d/gr3d_t30.c
@@ -22,8 +22,8 @@
 
 #include "nvhost_hwctx.h"
 #include "dev.h"
-#include "t20/hardware_t20.h"
-#include "t20/syncpt_t20.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
 #include "gr3d.h"
 
 #include <mach/gpufuse.h>
diff --git a/drivers/video/tegra/host/host1x/Makefile b/drivers/video/tegra/host/host1x/Makefile
new file mode 100644
index 000000000000..ba59d870d15b
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/Makefile
@@ -0,0 +1,13 @@
+GCOV_PROFILE := y
+
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+
+nvhost-host1x-objs  = \
+	host1x_syncpt.o \
+	host1x_cpuaccess.o \
+	host1x_channel.o \
+	host1x_intr.o \
+	host1x_cdma.o \
+	host1x_debug.o
+
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-host1x.o
diff --git a/drivers/video/tegra/host/t20/cdma_t20.c b/drivers/video/tegra/host/host1x/host1x_cdma.c
index a7bb45152b1b..008c8bfcde15 100644
--- a/drivers/video/tegra/host/t20/cdma_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.c
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/cdma_t20.c
+ * drivers/video/tegra/host/host1x/host1x_cdma.c
  *
  * Tegra Graphics Host Command DMA
  *
@@ -21,12 +21,12 @@
  */
 
 #include <linux/slab.h>
-#include "../nvhost_cdma.h"
-#include "../dev.h"
+#include "nvhost_cdma.h"
+#include "dev.h"
 
-#include "hardware_t20.h"
-#include "syncpt_t20.h"
-#include "cdma_t20.h"
+#include "host1x_hardware.h"
+#include "host1x_syncpt.h"
+#include "host1x_cdma.h"
 
 static inline u32 host1x_channel_dmactrl(int stop, int get_rst, int init_get)
 {
@@ -35,7 +35,7 @@ static inline u32 host1x_channel_dmactrl(int stop, int get_rst, int init_get)
 			| HOST1X_CREATE(CHANNEL_DMACTRL, DMAINITGET, init_get);
 }
 
-static void t20_cdma_timeout_handler(struct work_struct *work);
+static void cdma_timeout_handler(struct work_struct *work);
 
 /*
  * push_buffer
@@ -49,7 +49,7 @@ static void t20_cdma_timeout_handler(struct work_struct *work);
 /**
  * Reset to empty push buffer
  */
-static void t20_push_buffer_reset(struct push_buffer *pb)
+static void push_buffer_reset(struct push_buffer *pb)
 {
 	pb->fence = PUSH_BUFFER_SIZE - 8;
 	pb->cur = 0;
@@ -58,7 +58,7 @@ static void t20_push_buffer_reset(struct push_buffer *pb)
 /**
  * Init push buffer resources
  */
-static int t20_push_buffer_init(struct push_buffer *pb)
+static int push_buffer_init(struct push_buffer *pb)
 {
 	struct nvhost_cdma *cdma = pb_to_cdma(pb);
 	struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
@@ -96,7 +96,8 @@ static int t20_push_buffer_init(struct push_buffer *pb)
 		goto fail;
 
 	/* put the restart at the end of pushbuffer memory */
-	*(pb->mapped + (PUSH_BUFFER_SIZE >> 2)) = nvhost_opcode_restart(pb->phys);
+	*(pb->mapped + (PUSH_BUFFER_SIZE >> 2)) =
+		nvhost_opcode_restart(pb->phys);
 
 	return 0;
 
@@ -108,7 +109,7 @@ fail:
 /**
  * Clean up push buffer resources
  */
-static void t20_push_buffer_destroy(struct push_buffer *pb)
+static void push_buffer_destroy(struct push_buffer *pb)
 {
 	struct nvhost_cdma *cdma = pb_to_cdma(pb);
 	struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
@@ -133,7 +134,7 @@ static void t20_push_buffer_destroy(struct push_buffer *pb)
  * Push two words to the push buffer
  * Caller must ensure push buffer is not full
  */
-static void t20_push_buffer_push_to(struct push_buffer *pb,
+static void push_buffer_push_to(struct push_buffer *pb,
 		struct nvmap_client *client,
 		struct nvmap_handle *handle, u32 op1, u32 op2)
 {
@@ -152,13 +153,13 @@ static void t20_push_buffer_push_to(struct push_buffer *pb,
  * Pop a number of two word slots from the push buffer
  * Caller must ensure push buffer is not empty
  */
-static void t20_push_buffer_pop_from(struct push_buffer *pb,
+static void push_buffer_pop_from(struct push_buffer *pb,
 		unsigned int slots)
 {
 	/* Clear the nvmap references for old items from pb */
 	unsigned int i;
 	u32 fence_nvmap = pb->fence/8;
-	for(i = 0; i < slots; i++) {
+	for (i = 0; i < slots; i++) {
 		int cur_fence_nvmap = (fence_nvmap+i)
 				& (NVHOST_GATHER_QUEUE_SIZE - 1);
 		struct nvmap_client_handle *h =
@@ -173,12 +174,12 @@ static void t20_push_buffer_pop_from(struct push_buffer *pb,
 /**
  * Return the number of two word slots free in the push buffer
  */
-static u32 t20_push_buffer_space(struct push_buffer *pb)
+static u32 push_buffer_space(struct push_buffer *pb)
 {
 	return ((pb->fence - pb->cur) & (PUSH_BUFFER_SIZE - 1)) / 8;
 }
 
-static u32 t20_push_buffer_putptr(struct push_buffer *pb)
+static u32 push_buffer_putptr(struct push_buffer *pb)
 {
 	return pb->phys + pb->cur;
 }
@@ -193,7 +194,7 @@ static u32 t20_push_buffer_putptr(struct push_buffer *pb)
 /**
  * Init timeout and syncpt incr buffer resources
  */
-static int t20_cdma_timeout_init(struct nvhost_cdma *cdma,
+static int cdma_timeout_init(struct nvhost_cdma *cdma,
 				 u32 syncpt_id)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
@@ -251,7 +252,7 @@ static int t20_cdma_timeout_init(struct nvhost_cdma *cdma,
 	}
 	wmb();
 
-	INIT_DELAYED_WORK(&cdma->timeout.wq, t20_cdma_timeout_handler);
+	INIT_DELAYED_WORK(&cdma->timeout.wq, cdma_timeout_handler);
 	cdma->timeout.initialized = true;
 
 	return 0;
@@ -263,7 +264,7 @@ fail:
 /**
  * Clean up timeout syncpt buffer resources
  */
-static void t20_cdma_timeout_destroy(struct nvhost_cdma *cdma)
+static void cdma_timeout_destroy(struct nvhost_cdma *cdma)
 {
 	struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
 	struct syncpt_buffer *sb = &cdma->syncpt_buffer;
@@ -289,7 +290,7 @@ static void t20_cdma_timeout_destroy(struct nvhost_cdma *cdma)
 /**
  * Increment timedout buffer's syncpt via CPU.
  */
-static void t20_cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
+static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
 				u32 syncpt_incrs, u32 syncval, u32 nr_slots)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
@@ -329,7 +330,7 @@ static void t20_cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
  * whether there's a CTXSAVE that should be still executed (for the
  * preceding HW ctx).
  */
-static void t20_cdma_timeout_pb_incr(struct nvhost_cdma *cdma, u32 getptr,
+static void cdma_timeout_pb_incr(struct nvhost_cdma *cdma, u32 getptr,
 				u32 syncpt_incrs, u32 nr_slots,
 				bool exec_ctxsave)
 {
@@ -393,7 +394,7 @@ static void t20_cdma_timeout_pb_incr(struct nvhost_cdma *cdma, u32 getptr,
 /**
  * Start channel DMA
  */
-static void t20_cdma_start(struct nvhost_cdma *cdma)
+static void cdma_start(struct nvhost_cdma *cdma)
 {
 	void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
 
@@ -423,11 +424,11 @@ static void t20_cdma_start(struct nvhost_cdma *cdma)
 }
 
 /**
- * Similar to t20_cdma_start(), but rather than starting from an idle
+ * Similar to cdma_start(), but rather than starting from an idle
  * state (where DMA GET is set to DMA PUT), on a timeout we restore
  * DMA GET from an explicit value (so DMA may again be pending).
  */
-static void t20_cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
+static void cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
 	void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
@@ -472,7 +473,7 @@ static void t20_cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 /**
  * Kick channel DMA into action by writing its PUT offset (if it has changed)
  */
-static void t20_cdma_kick(struct nvhost_cdma *cdma)
+static void cdma_kick(struct nvhost_cdma *cdma)
 {
 	u32 put;
 	BUG_ON(!cdma_pb_op(cdma).putptr);
@@ -487,7 +488,7 @@ static void t20_cdma_kick(struct nvhost_cdma *cdma)
 	}
 }
 
-static void t20_cdma_stop(struct nvhost_cdma *cdma)
+static void cdma_stop(struct nvhost_cdma *cdma)
 {
 	void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
 
@@ -504,7 +505,7 @@ static void t20_cdma_stop(struct nvhost_cdma *cdma)
 /**
  * Retrieve the op pair at a slot offset from a DMA address
  */
-void t20_cdma_peek(struct nvhost_cdma *cdma,
+void cdma_peek(struct nvhost_cdma *cdma,
 			  u32 dmaget, int slot, u32 *out)
 {
 	u32 offset = dmaget - cdma->push_buffer.phys;
@@ -519,7 +520,7 @@ void t20_cdma_peek(struct nvhost_cdma *cdma,
  * Stops both channel's command processor and CDMA immediately.
  * Also, tears down the channel and resets corresponding module.
  */
-void t20_cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
+void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
 	struct nvhost_channel *ch = cdma_to_channel(cdma);
@@ -551,7 +552,7 @@ void t20_cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 	cdma->torndown = true;
 }
 
-void t20_cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
+void cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
 {
 	struct nvhost_master *dev = cdma_to_dev(cdma);
 	struct nvhost_channel *ch = cdma_to_channel(cdma);
@@ -568,7 +569,7 @@ void t20_cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
 	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
 
 	cdma->torndown = false;
-	t20_cdma_timeout_restart(cdma, getptr);
+	cdma_timeout_restart(cdma, getptr);
 }
 
 /**
@@ -576,7 +577,7 @@ void t20_cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
  * exceeded its TTL and the userctx should be timed out and remaining
  * submits already issued cleaned up (future submits return an error).
  */
-static void t20_cdma_timeout_handler(struct work_struct *work)
+static void cdma_timeout_handler(struct work_struct *work)
 {
 	struct nvhost_cdma *cdma;
 	struct nvhost_master *dev;
@@ -640,28 +641,28 @@ static void t20_cdma_timeout_handler(struct work_struct *work)
 	mutex_unlock(&cdma->lock);
 }
 
-int nvhost_init_t20_cdma_support(struct nvhost_master *host)
+int host1x_init_cdma_support(struct nvhost_master *host)
 {
-	host->op.cdma.start = t20_cdma_start;
-	host->op.cdma.stop = t20_cdma_stop;
-	host->op.cdma.kick = t20_cdma_kick;
+	host->op.cdma.start = cdma_start;
+	host->op.cdma.stop = cdma_stop;
+	host->op.cdma.kick = cdma_kick;
 
-	host->op.cdma.timeout_init = t20_cdma_timeout_init;
-	host->op.cdma.timeout_destroy = t20_cdma_timeout_destroy;
-	host->op.cdma.timeout_teardown_begin = t20_cdma_timeout_teardown_begin;
-	host->op.cdma.timeout_teardown_end = t20_cdma_timeout_teardown_end;
-	host->op.cdma.timeout_cpu_incr = t20_cdma_timeout_cpu_incr;
-	host->op.cdma.timeout_pb_incr = t20_cdma_timeout_pb_incr;
+	host->op.cdma.timeout_init = cdma_timeout_init;
+	host->op.cdma.timeout_destroy = cdma_timeout_destroy;
+	host->op.cdma.timeout_teardown_begin = cdma_timeout_teardown_begin;
+	host->op.cdma.timeout_teardown_end = cdma_timeout_teardown_end;
+	host->op.cdma.timeout_cpu_incr = cdma_timeout_cpu_incr;
+	host->op.cdma.timeout_pb_incr = cdma_timeout_pb_incr;
 
 	host->sync_queue_size = NVHOST_SYNC_QUEUE_SIZE;
 
-	host->op.push_buffer.reset = t20_push_buffer_reset;
-	host->op.push_buffer.init = t20_push_buffer_init;
-	host->op.push_buffer.destroy = t20_push_buffer_destroy;
-	host->op.push_buffer.push_to = t20_push_buffer_push_to;
-	host->op.push_buffer.pop_from = t20_push_buffer_pop_from;
-	host->op.push_buffer.space = t20_push_buffer_space;
-	host->op.push_buffer.putptr = t20_push_buffer_putptr;
+	host->op.push_buffer.reset = push_buffer_reset;
+	host->op.push_buffer.init = push_buffer_init;
+	host->op.push_buffer.destroy = push_buffer_destroy;
+	host->op.push_buffer.push_to = push_buffer_push_to;
+	host->op.push_buffer.pop_from = push_buffer_pop_from;
+	host->op.push_buffer.space = push_buffer_space;
+	host->op.push_buffer.putptr = push_buffer_putptr;
 
 	return 0;
 }
diff --git a/drivers/video/tegra/host/t20/cdma_t20.h b/drivers/video/tegra/host/host1x/host1x_cdma.h
index 26b065548f34..e66da0f19772 100644
--- a/drivers/video/tegra/host/t20/cdma_t20.h
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.h
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/cdma_t20.h
+ * drivers/video/tegra/host/host1x/host1x_cdma.h
  *
  * Tegra Graphics Host Channel
  *
@@ -20,8 +20,8 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#ifndef __NVHOST_CDMA_T20_H
-#define __NVHOST_CDMA_T20_H
+#ifndef __NVHOST_HOST1X_HOST1X_CDMA_H
+#define __NVHOST_HOST1X_HOST1X_CDMA_H
 
 /* Size of the sync queue. If it is too small, we won't be able to queue up
  * many command buffers. If it is too large, we waste memory. */
@@ -38,4 +38,6 @@
  * and replaces the original timed out contexts GATHER slots */
 #define SYNCPT_INCR_BUFFER_SIZE_WORDS   (4096 / sizeof(u32))
 
+int host1x_init_cdma_support(struct nvhost_master *);
+
 #endif
diff --git a/drivers/video/tegra/host/t20/channel_t20.c b/drivers/video/tegra/host/host1x/host1x_channel.c
index 28c7dc013c60..f5f36ca6a001 100644
--- a/drivers/video/tegra/host/t20/channel_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_channel.c
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/channel_t20.c
+ * drivers/video/tegra/host/host1x/channel_host1x.c
  *
  * Tegra Graphics Host Channel
  *
@@ -20,160 +20,20 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#include "../nvhost_channel.h"
-#include "../dev.h"
-#include "../nvhost_hwctx.h"
+#include "nvhost_channel.h"
+#include "dev.h"
+#include "nvhost_hwctx.h"
 #include <trace/events/nvhost.h>
-#include <mach/powergate.h>
 #include <linux/slab.h>
 
-#include "channel_t20.h"
-#include "syncpt_t20.h"
-#include "../gr3d/gr3d_t20.h"
-
-#include "../gr3d/gr3d.h"
-#include "../mpe/mpe.h"
-#include "../nvhost_intr.h"
-
-#define NVHOST_NUMCHANNELS (NV_HOST1X_CHANNELS - 1)
-
-#define NVMODMUTEX_2D_FULL   (1)
-#define NVMODMUTEX_2D_SIMPLE (2)
-#define NVMODMUTEX_2D_SB_A   (3)
-#define NVMODMUTEX_2D_SB_B   (4)
-#define NVMODMUTEX_3D        (5)
-#define NVMODMUTEX_DISPLAYA  (6)
-#define NVMODMUTEX_DISPLAYB  (7)
-#define NVMODMUTEX_VI        (8)
-#define NVMODMUTEX_DSI       (9)
-#define NV_FIFO_READ_TIMEOUT 200000
-
-const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
-{
-	/* channel 0 */
-	.name	       = "display",
-	.syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
-			 BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
-			 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
-			 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
-	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 1 */
-	.name	       = "gr3d",
-	.syncpts       = BIT(NVSYNCPT_3D),
-	.waitbases     = BIT(NVWAITBASE_3D),
-	.modulemutexes = BIT(NVMODMUTEX_3D),
-	.class	       = NV_GRAPHICS_3D_CLASS_ID,
-	.module        = {
-			.prepare_poweroff = nvhost_gr3d_prepare_power_off,
-			.clocks = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
-			.powergate_ids = {TEGRA_POWERGATE_3D, -1},
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 2 */
-	.name	       = "gr2d",
-	.syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-	.waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
-	.module        = {
-			.clocks = {{"gr2d", UINT_MAX} ,
-					{"epp", UINT_MAX} ,
-					{"emc", UINT_MAX} },
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			.clockgate_delay = 0,
-			}
-},
-{
-	/* channel 3 */
-	.name	 = "isp",
-	.syncpts = 0,
-	.module         = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 4 */
-	.name	       = "vi",
-	.syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-			 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-			 BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-			 BIT(NVSYNCPT_VI_ISP_4),
-	.modulemutexes = BIT(NVMODMUTEX_VI),
-	.exclusive     = true,
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			}
-},
-{
-	/* channel 5 */
-	.name	       = "mpe",
-	.syncpts       = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
-			 BIT(NVSYNCPT_MPE_WR_SAFE),
-	.waitbases     = BIT(NVWAITBASE_MPE),
-	.class	       = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
-	.waitbasesync  = true,
-	.keepalive     = true,
-	.module        = {
-			.prepare_poweroff = nvhost_mpe_prepare_power_off,
-			.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
-			.powergate_ids = {TEGRA_POWERGATE_MPE, -1},
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 6 */
-	.name	       = "dsi",
-	.syncpts       = BIT(NVSYNCPT_DSI),
-	.modulemutexes = BIT(NVMODMUTEX_DSI),
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-}};
-
-static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
-{
-	p += NV_HOST1X_CHANNEL0_BASE;
-	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
-	return p;
-}
-
-static inline int t20_nvhost_hwctx_handler_init(
-	struct nvhost_hwctx_handler *h,
-	const char *module)
-{
-	if (strcmp(module, "gr3d") == 0)
-		return nvhost_gr3d_t20_ctxhandler_init(h);
-	else if (strcmp(module, "mpe") == 0)
-		return nvhost_mpe_ctxhandler_init(h);
-	return 0;
-}
-
-static int t20_channel_init(struct nvhost_channel *ch,
-			    struct nvhost_master *dev, int index)
-{
-	ch->dev = dev;
-	ch->chid = index;
-	ch->desc = nvhost_t20_channelmap + index;
-	mutex_init(&ch->reflock);
-	mutex_init(&ch->submitlock);
-
-	ch->aperture = t20_channel_aperture(dev->aperture, index);
+#include "host1x_syncpt.h"
+#include "host1x_channel.h"
+#include "host1x_hardware.h"
+#include "nvhost_intr.h"
 
-	return t20_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->desc->name);
-}
+#define NV_FIFO_READ_TIMEOUT 200000
 
-static void t20_channel_sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val)
+static void sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val)
 {
 	unsigned long waitbase;
 	unsigned long int waitbase_mask = ch->desc->waitbases;
@@ -188,7 +48,7 @@ static void t20_channel_sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val
 	}
 }
 
-static int t20_channel_submit(struct nvhost_job *job)
+int host1x_channel_submit(struct nvhost_job *job)
 {
 	struct nvhost_hwctx *hwctx_to_save = NULL;
 	struct nvhost_channel *channel = job->ch;
@@ -261,7 +121,7 @@ static int t20_channel_submit(struct nvhost_job *job)
 		goto done;
 	}
 
-	t20_channel_sync_waitbases(channel, job->syncpt_end);
+	sync_waitbases(channel, job->syncpt_end);
 
 	/* context switch */
 	if (channel->cur_ctx != job->hwctx) {
@@ -403,7 +263,7 @@ done:
 	return err;
 }
 
-static int t20_channel_read_3d_reg(
+int host1x_channel_read_3d_reg(
 	struct nvhost_channel *channel,
 	struct nvhost_hwctx *hwctx,
 	u32 offset,
@@ -553,7 +413,7 @@ static int t20_channel_read_3d_reg(
 	nvhost_intr_put_ref(&channel->dev->intr, ref);
 
 	/* Read the register value from FIFO */
-	err = nvhost_drain_read_fifo(channel->aperture,
+	err = host1x_drain_read_fifo(channel->aperture,
 		value, 1, &pending);
 
 	/* Indicate we've read the value */
@@ -576,19 +436,7 @@ done:
 }
 
 
-int nvhost_init_t20_channel_support(struct nvhost_master *host)
-{
-	host->nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
-	host->nb_channels =  NVHOST_NUMCHANNELS;
-
-	host->op.channel.init = t20_channel_init;
-	host->op.channel.submit = t20_channel_submit;
-	host->op.channel.read3dreg = t20_channel_read_3d_reg;
-
-	return 0;
-}
-
-int nvhost_drain_read_fifo(void __iomem *chan_regs,
+int host1x_drain_read_fifo(void __iomem *chan_regs,
 	u32 *ptr, unsigned int count, unsigned int *pending)
 {
 	unsigned int entries = *pending;
@@ -629,3 +477,94 @@ int nvhost_drain_read_fifo(void __iomem *chan_regs,
 
 	return 0;
 }
+
+int host1x_save_context(struct nvhost_module *mod, u32 syncpt_id)
+{
+	struct nvhost_channel *ch =
+			container_of(mod, struct nvhost_channel, mod);
+	struct nvhost_hwctx *hwctx_to_save;
+	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+	u32 syncpt_incrs, syncpt_val;
+	int err = 0;
+	void *ref;
+	void *ctx_waiter = NULL, *wakeup_waiter = NULL;
+	struct nvhost_job *job;
+
+	ctx_waiter = nvhost_intr_alloc_waiter();
+	wakeup_waiter = nvhost_intr_alloc_waiter();
+	if (!ctx_waiter || !wakeup_waiter) {
+		err = -ENOMEM;
+		goto done;
+	}
+
+	if (mod->desc->busy)
+		mod->desc->busy(mod);
+
+	mutex_lock(&ch->submitlock);
+	hwctx_to_save = ch->cur_ctx;
+	if (!hwctx_to_save) {
+		mutex_unlock(&ch->submitlock);
+		goto done;
+	}
+
+	job = nvhost_job_alloc(ch, hwctx_to_save,
+			NULL,
+			ch->dev->nvmap, 0, 0);
+	if (IS_ERR_OR_NULL(job)) {
+		err = PTR_ERR(job);
+		mutex_unlock(&ch->submitlock);
+		goto done;
+	}
+
+	hwctx_to_save->valid = true;
+	ch->ctxhandler.get(hwctx_to_save);
+	ch->cur_ctx = NULL;
+
+	syncpt_incrs = hwctx_to_save->save_incrs;
+	syncpt_val = nvhost_syncpt_incr_max(&ch->dev->syncpt,
+					syncpt_id, syncpt_incrs);
+
+	job->syncpt_id = syncpt_id;
+	job->syncpt_incrs = syncpt_incrs;
+	job->syncpt_end = syncpt_val;
+
+	err = nvhost_cdma_begin(&ch->cdma, job);
+	if (err) {
+		mutex_unlock(&ch->submitlock);
+		goto done;
+	}
+
+	ch->ctxhandler.save_push(&ch->cdma, hwctx_to_save);
+	nvhost_cdma_end(&ch->cdma, job);
+	nvhost_job_put(job);
+	job = NULL;
+
+	err = nvhost_intr_add_action(&ch->dev->intr, syncpt_id,
+			syncpt_val - syncpt_incrs + hwctx_to_save->save_thresh,
+			NVHOST_INTR_ACTION_CTXSAVE, hwctx_to_save,
+			ctx_waiter,
+			NULL);
+	ctx_waiter = NULL;
+	WARN(err, "Failed to set context save interrupt");
+
+	err = nvhost_intr_add_action(&ch->dev->intr, syncpt_id, syncpt_val,
+			NVHOST_INTR_ACTION_WAKEUP, &wq,
+			wakeup_waiter,
+			&ref);
+	wakeup_waiter = NULL;
+	WARN(err, "Failed to set wakeup interrupt");
+	wait_event(wq,
+		nvhost_syncpt_min_cmp(&ch->dev->syncpt,
+				syncpt_id, syncpt_val));
+
+	nvhost_intr_put_ref(&ch->dev->intr, ref);
+
+	nvhost_cdma_update(&ch->cdma);
+
+	mutex_unlock(&ch->submitlock);
+
+done:
+	kfree(ctx_waiter);
+	kfree(wakeup_waiter);
+	return err;
+}
diff --git a/drivers/video/tegra/host/t20/channel_t20.h b/drivers/video/tegra/host/host1x/host1x_channel.h
index 13ccfd004b57..3c4cf4f9cbcd 100644
--- a/drivers/video/tegra/host/t20/channel_t20.h
+++ b/drivers/video/tegra/host/host1x/host1x_channel.h
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/channel_t20.h
+ * drivers/video/tegra/host/host1x/host1x_channel.h
  *
  * Tegra Graphics Host Channel
  *
@@ -20,16 +20,27 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#ifndef __NVHOST_CHANNEL_T20_H
-#define __NVHOST_CHANNEL_T20_H
+#ifndef __NVHOST_HOST1X_CHANNEL_H
+#define __NVHOST_HOST1X_CHANNEL_H
 
-#include "hardware_t20.h"
-#include "../nvhost_channel.h"
+struct nvhost_job;
+struct nvhost_channel;
+struct nvhost_hwctx;
 
-extern const struct nvhost_channeldesc nvhost_t20_channelmap[];
+/*  Submit job to a host1x client */
+int host1x_channel_submit(struct nvhost_job *job);
+
+/*  Read 3d register via FIFO */
+int host1x_channel_read_3d_reg(
+	struct nvhost_channel *channel,
+	struct nvhost_hwctx *hwctx,
+	u32 offset,
+	u32 *value);
 
 /* Reads words from FIFO */
-int nvhost_drain_read_fifo(void __iomem *chan_regs,
+int host1x_drain_read_fifo(void __iomem *chan_regs,
 		u32 *ptr, unsigned int count, unsigned int *pending);
 
+int host1x_save_context(struct nvhost_module *mod, u32 syncpt_id);
+
 #endif
diff --git a/drivers/video/tegra/host/t20/cpuaccess_t20.c b/drivers/video/tegra/host/host1x/host1x_cpuaccess.c
index f6bb76f4165a..927f4ca85bdc 100644
--- a/drivers/video/tegra/host/t20/cpuaccess_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_cpuaccess.c
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/cpuaccess_t20.c
+ * drivers/video/tegra/host/host1x/host1x_cpuaccess.c
  *
  * Tegra Graphics Host Cpu Register Access
  *
@@ -20,10 +20,9 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#include "../nvhost_cpuaccess.h"
-#include "../dev.h"
-
-#include "hardware_t20.h"
+#include "nvhost_cpuaccess.h"
+#include "dev.h"
+#include "host1x_hardware.h"
 
 static int t20_cpuaccess_mutex_try_lock(struct nvhost_cpuaccess *ctx,
 					unsigned int idx)
diff --git a/drivers/video/tegra/host/t20/debug_t20.c b/drivers/video/tegra/host/host1x/host1x_debug.c
index 9ce8efc95570..f47a2a5c275f 100644
--- a/drivers/video/tegra/host/t20/debug_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_debug.c
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/debug_t20.c
+ * drivers/video/tegra/host/host1x/host1x_debug.c
  *
  * Copyright (C) 2010 Google, Inc.
  * Author: Erik Gilling <konkers@android.com>
@@ -23,13 +23,13 @@
 
 #include <linux/io.h>
 
-#include "../dev.h"
-#include "../debug.h"
-#include "../nvhost_cdma.h"
+#include "dev.h"
+#include "debug.h"
+#include "nvhost_cdma.h"
 #include "../../nvmap/nvmap.h"
 
-#include "hardware_t20.h"
-#include "cdma_t20.h"
+#include "host1x_hardware.h"
+#include "host1x_cdma.h"
 
 #define NVHOST_DEBUG_MAX_PAGE_OFFSET 102400
 
@@ -48,22 +48,26 @@ static int show_channel_command(struct output *o, u32 addr, u32 val, int *count)
 	case 0x0:
 		mask = val & 0x3f;
 		if (mask) {
-			nvhost_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
-				   val >> 6 & 0x3ff, val >> 16 & 0xfff, mask);
+			nvhost_debug_output(o,
+				"SETCL(class=%03x, offset=%03x, mask=%02x, [",
+				val >> 6 & 0x3ff, val >> 16 & 0xfff, mask);
 			*count = hweight8(mask);
 			return NVHOST_DBG_STATE_DATA;
 		} else {
-			nvhost_debug_output(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
+			nvhost_debug_output(o, "SETCL(class=%03x)\n",
+				val >> 6 & 0x3ff);
 			return NVHOST_DBG_STATE_CMD;
 		}
 
 	case 0x1:
-		nvhost_debug_output(o, "INCR(offset=%03x, [", val >> 16 & 0xfff);
+		nvhost_debug_output(o, "INCR(offset=%03x, [",
+			val >> 16 & 0xfff);
 		*count = val & 0xffff;
 		return NVHOST_DBG_STATE_DATA;
 
 	case 0x2:
-		nvhost_debug_output(o, "NONINCR(offset=%03x, [", val >> 16 & 0xfff);
+		nvhost_debug_output(o, "NONINCR(offset=%03x, [",
+			val >> 16 & 0xfff);
 		*count = val & 0xffff;
 		return NVHOST_DBG_STATE_DATA;
 
@@ -85,17 +89,19 @@ static int show_channel_command(struct output *o, u32 addr, u32 val, int *count)
 
 	case 0x6:
 		nvhost_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
-			   val >> 16 & 0xfff, val >> 15 & 0x1, val >> 14 & 0x1,
-			   val & 0x3fff);
+			val >> 16 & 0xfff, val >> 15 & 0x1, val >> 14 & 0x1,
+			val & 0x3fff);
 		*count = val & 0x3fff; /* TODO: insert */
 		return NVHOST_DBG_STATE_GATHER;
 
 	case 0xe:
 		subop = val >> 24 & 0xf;
 		if (subop == 0)
-			nvhost_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n", val & 0xff);
+			nvhost_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n",
+				val & 0xff);
 		else if (subop == 1)
-			nvhost_debug_output(o, "RELEASE_MLOCK(index=%d)\n", val & 0xff);
+			nvhost_debug_output(o, "RELEASE_MLOCK(index=%d)\n",
+				val & 0xff);
 		else
 			nvhost_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val);
 		return NVHOST_DBG_STATE_CMD;
@@ -310,7 +316,8 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 	nvhost_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
 
 	cdma_peek(cdma, dmaget, -1, pbw);
-	show_channel_pair(o, previous_oppair(cdma, dmaget), pbw[0], pbw[1], &channel->cdma);
+	show_channel_pair(o, previous_oppair(cdma, dmaget),
+		pbw[0], pbw[1], &channel->cdma);
 	nvhost_debug_output(o, "\n");
 }
 
diff --git a/drivers/video/tegra/host/t20/hardware_t20.h b/drivers/video/tegra/host/host1x/host1x_hardware.h
index c36d3a94932f..da0cf18b6a2e 100644
--- a/drivers/video/tegra/host/t20/hardware_t20.h
+++ b/drivers/video/tegra/host/host1x/host1x_hardware.h
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/hardware_t20.h
+ * drivers/video/tegra/host/host1x/host1x_hardware.h
  *
  * Tegra Graphics Host Register Offsets
  *
@@ -20,8 +20,8 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#ifndef __NVHOST_HARDWARE_T20_H
-#define __NVHOST_HARDWARE_T20_H
+#ifndef __NVHOST_HOST1X_HOST1X_HARDWARE_H
+#define __NVHOST_HOST1X_HOST1X_HARDWARE_H
 
 #include <linux/types.h>
 #include <linux/bitops.h>
@@ -273,4 +273,4 @@ static inline u32 nvhost_mask2(unsigned x, unsigned y)
 	return 1 | (1 << (y - x));
 }
 
-#endif /* __NVHOST_HARDWARE_T20_H */
+#endif
diff --git a/drivers/video/tegra/host/t20/intr_t20.c b/drivers/video/tegra/host/host1x/host1x_intr.c
index 499246d6fd81..a2a78d79c704 100644
--- a/drivers/video/tegra/host/t20/intr_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_intr.c
@@ -1,5 +1,5 @@
 /*
- * drivers/video/tegra/host/t20/intr_t20.c
+ * drivers/video/tegra/host/host1x/host1x_intr.c
  *
  * Tegra Graphics Host Interrupt Management
  *
@@ -23,10 +23,9 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include "../nvhost_intr.h"
-#include "../dev.h"
-
-#include "hardware_t20.h"
+#include "nvhost_intr.h"
+#include "dev.h"
+#include "host1x_hardware.h"
 
 
 /*** HW host sync management ***/
@@ -54,7 +53,8 @@ static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
 	writel(cpm, sync_regs + HOST1X_SYNC_USEC_CLK);
 }
 
-static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr, u32 id, u32 thresh)
+static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
+	u32 id, u32 thresh)
 {
 	struct nvhost_master *dev = intr_to_dev(intr);
 	void __iomem *sync_regs = dev->sync_aperture;
@@ -190,7 +190,8 @@ static int t20_request_syncpt_irq(struct nvhost_intr_syncpt *syncpt)
 		return 0;
 
 	err = request_threaded_irq(syncpt->irq,
-				   t20_intr_syncpt_thresh_isr, nvhost_syncpt_thresh_fn,
+				   t20_intr_syncpt_thresh_isr,
+				   nvhost_syncpt_thresh_fn,
 				   0, syncpt->thresh_irq_name, syncpt);
 	if (err)
 		return err;
diff --git a/drivers/video/tegra/host/t20/syncpt_t20.c b/drivers/video/tegra/host/host1x/host1x_syncpt.c
index 259e80fd25f6..ecfa08c31e94 100644
--- a/drivers/video/tegra/host/t20/syncpt_t20.c
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.c
@@ -1,7 +1,7 @@
 /*
- * drivers/video/tegra/host/t20/syncpt_t20.c
+ * drivers/video/tegra/host/host1x/host1x_syncpt.c
  *
- * Tegra Graphics Host Syncpoints for T20
+ * Tegra Graphics Host Syncpoints for HOST1X
  *
  * Copyright (c) 2010-2011, NVIDIA Corporation.
  *
@@ -21,11 +21,10 @@
  */
 
 #include <linux/nvhost_ioctl.h>
-#include "../nvhost_syncpt.h"
-#include "../dev.h"
-
-#include "syncpt_t20.h"
-#include "hardware_t20.h"
+#include "nvhost_syncpt.h"
+#include "dev.h"
+#include "host1x_syncpt.h"
+#include "host1x_hardware.h"
 
 /**
  * Write the current syncpoint value back to hw.
@@ -221,7 +220,7 @@ static void t20_syncpt_debug(struct nvhost_syncpt *sp)
 	}
 }
 
-int nvhost_init_t20_syncpt_support(struct nvhost_master *host)
+int host1x_init_syncpt_support(struct nvhost_master *host)
 {
 
 	host->sync_aperture = host->aperture +
diff --git a/drivers/video/tegra/host/t20/syncpt_t20.h b/drivers/video/tegra/host/host1x/host1x_syncpt.h
index 4dfd75f937fc..324ca8b45e49 100644
--- a/drivers/video/tegra/host/t20/syncpt_t20.h
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.h
@@ -1,7 +1,7 @@
 /*
- * drivers/video/tegra/host/t20/syncpt_t20.h
+ * drivers/video/tegra/host/host1x/host1x_syncpt.h
  *
- * Tegra Graphics Host Syncpoints for T20
+ * Tegra Graphics Host Syncpoints for HOST1X
  *
  * Copyright (c) 2010-2011, NVIDIA Corporation.
  *
@@ -20,8 +20,8 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#ifndef __NVHOST_SYNCPT_T20_H
-#define __NVHOST_SYNCPT_T20_H
+#ifndef __NVHOST_HOST1X_HOST1X_SYNCPT_H
+#define __NVHOST_HOST1X_HOST1X_SYNCPT_H
 
 #define NVSYNCPT_DISP0_A		     (8)
 #define NVSYNCPT_DISP1_A		     (9)
@@ -73,6 +73,7 @@
 #define NVWAITBASE_MPE  (4)
 
 struct nvhost_master;
-int nvhost_t20_init_syncpt(struct nvhost_master *host);
+int host1x_init_syncpt(struct nvhost_master *host);
+int host1x_init_syncpt_support(struct nvhost_master *host);
 
-#endif /* __NVHOST_SYNCPT_T20_H */
+#endif
diff --git a/drivers/video/tegra/host/mpe/mpe.c b/drivers/video/tegra/host/mpe/mpe.c
index 763cc5a7e070..3e89e6989e44 100644
--- a/drivers/video/tegra/host/mpe/mpe.c
+++ b/drivers/video/tegra/host/mpe/mpe.c
@@ -22,9 +22,9 @@
 
 #include "nvhost_hwctx.h"
 #include "dev.h"
-#include "t20/hardware_t20.h"
-#include "t20/channel_t20.h"
-#include "t20/syncpt_t20.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_syncpt.h"
 #include "t20/t20.h"
 #include <linux/slab.h>
 
@@ -399,7 +399,7 @@ static u32 *save_regs(u32 *ptr, unsigned int *pending,
 		u32 count = regs->count;
 		++ptr; /* restore incr */
 		if (regs->type == HWCTX_REGINFO_NORMAL) {
-			nvhost_drain_read_fifo(channel->aperture,
+			host1x_drain_read_fifo(channel->aperture,
 						ptr, count, pending);
 			ptr += count;
 		} else {
@@ -408,7 +408,7 @@ static u32 *save_regs(u32 *ptr, unsigned int *pending,
 				BUG_ON(msi->out_pos >= NR_WRITEBACKS);
 				word = msi->out[msi->out_pos++];
 			} else {
-				nvhost_drain_read_fifo(channel->aperture,
+				host1x_drain_read_fifo(channel->aperture,
 							&word, 1, pending);
 				if (regs->type == HWCTX_REGINFO_STASH) {
 					BUG_ON(msi->in_pos >= NR_STASHES);
@@ -429,7 +429,7 @@ static u32 *save_ram(u32 *ptr, unsigned int *pending,
 {
 	int err = 0;
 	ptr += RESTORE_RAM_SIZE;
-	err = nvhost_drain_read_fifo(channel->aperture, ptr, words, pending);
+	err = host1x_drain_read_fifo(channel->aperture, ptr, words, pending);
 	WARN_ON(err);
 	return ptr + words;
 }
@@ -566,5 +566,5 @@ int __init nvhost_mpe_ctxhandler_init(struct nvhost_hwctx_handler *h)
 
 int nvhost_mpe_prepare_power_off(struct nvhost_module *mod)
 {
-	return nvhost_t20_save_context(mod, NVSYNCPT_MPE);
+	return host1x_save_context(mod, NVSYNCPT_MPE);
 }
diff --git a/drivers/video/tegra/host/t20/Makefile b/drivers/video/tegra/host/t20/Makefile
index 8fde1a622078..c2ade9bf925b 100644
--- a/drivers/video/tegra/host/t20/Makefile
+++ b/drivers/video/tegra/host/t20/Makefile
@@ -1,12 +1,8 @@
 GCOV_PROFILE := y
 
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+
 nvhost-t20-objs  = \
-	t20.o \
-	syncpt_t20.o \
-	cpuaccess_t20.o \
-	channel_t20.o \
-	intr_t20.o \
-	cdma_t20.o \
-	debug_t20.o
+	t20.o
 
 obj-$(CONFIG_TEGRA_GRHOST) += nvhost-t20.o
diff --git a/drivers/video/tegra/host/t20/t20.c b/drivers/video/tegra/host/t20/t20.c
index e523c27a0fb0..510e0eb5f2df 100644
--- a/drivers/video/tegra/host/t20/t20.c
+++ b/drivers/video/tegra/host/t20/t20.c
@@ -21,9 +21,28 @@
  */
 
 #include <linux/slab.h>
-#include "../dev.h"
-
+#include <mach/powergate.h>
+#include "dev.h"
 #include "t20.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_syncpt.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_cdma.h"
+#include "gr3d/gr3d.h"
+#include "gr3d/gr3d_t20.h"
+#include "mpe/mpe.h"
+
+#define NVMODMUTEX_2D_FULL   (1)
+#define NVMODMUTEX_2D_SIMPLE (2)
+#define NVMODMUTEX_2D_SB_A   (3)
+#define NVMODMUTEX_2D_SB_B   (4)
+#define NVMODMUTEX_3D        (5)
+#define NVMODMUTEX_DISPLAYA  (6)
+#define NVMODMUTEX_DISPLAYB  (7)
+#define NVMODMUTEX_VI        (8)
+#define NVMODMUTEX_DSI       (9)
+
+#define NVHOST_NUMCHANNELS (NV_HOST1X_CHANNELS - 1)
 
 static struct nvhost_device devices[] = {
 	{.name   = "gr3d", .id = -1 },
@@ -34,6 +53,143 @@ static struct nvhost_device devices[] = {
 	{.name = "dsi", .id = -1 }
 };
 
+const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
+{
+	/* channel 0 */
+	.name	       = "display",
+	.syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
+			 BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
+			 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
+			 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
+	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 1 */
+	.name	       = "gr3d",
+	.syncpts       = BIT(NVSYNCPT_3D),
+	.waitbases     = BIT(NVWAITBASE_3D),
+	.modulemutexes = BIT(NVMODMUTEX_3D),
+	.class	       = NV_GRAPHICS_3D_CLASS_ID,
+	.module        = {
+			.prepare_poweroff = nvhost_gr3d_prepare_power_off,
+			.clocks = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
+			.powergate_ids = {TEGRA_POWERGATE_3D, -1},
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 2 */
+	.name	       = "gr2d",
+	.syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+	.waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
+	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
+			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+	.module        = {
+			.clocks = {{"gr2d", UINT_MAX} ,
+					{"epp", UINT_MAX} ,
+					{"emc", UINT_MAX} },
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			.clockgate_delay = 0,
+			}
+},
+{
+	/* channel 3 */
+	.name	 = "isp",
+	.syncpts = 0,
+	.module         = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 4 */
+	.name	       = "vi",
+	.syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
+			 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
+			 BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
+			 BIT(NVSYNCPT_VI_ISP_4),
+	.modulemutexes = BIT(NVMODMUTEX_VI),
+	.exclusive     = true,
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			}
+},
+{
+	/* channel 5 */
+	.name	       = "mpe",
+	.syncpts       = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
+			 BIT(NVSYNCPT_MPE_WR_SAFE),
+	.waitbases     = BIT(NVWAITBASE_MPE),
+	.class	       = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+	.waitbasesync  = true,
+	.keepalive     = true,
+	.module        = {
+			.prepare_poweroff = nvhost_mpe_prepare_power_off,
+			.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
+			.powergate_ids = {TEGRA_POWERGATE_MPE, -1},
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 6 */
+	.name	       = "dsi",
+	.syncpts       = BIT(NVSYNCPT_DSI),
+	.modulemutexes = BIT(NVMODMUTEX_DSI),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+} };
+
+static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
+{
+	p += NV_HOST1X_CHANNEL0_BASE;
+	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
+	return p;
+}
+
+static inline int t20_nvhost_hwctx_handler_init(
+	struct nvhost_hwctx_handler *h,
+	const char *module)
+{
+	if (strcmp(module, "gr3d") == 0)
+		return nvhost_gr3d_t20_ctxhandler_init(h);
+	else if (strcmp(module, "mpe") == 0)
+		return nvhost_mpe_ctxhandler_init(h);
+	return 0;
+}
+
+static int t20_channel_init(struct nvhost_channel *ch,
+			    struct nvhost_master *dev, int index)
+{
+	ch->dev = dev;
+	ch->chid = index;
+	ch->desc = nvhost_t20_channelmap + index;
+	mutex_init(&ch->reflock);
+	mutex_init(&ch->submitlock);
+
+	ch->aperture = t20_channel_aperture(dev->aperture, index);
+
+	return t20_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->desc->name);
+}
+
+int nvhost_init_t20_channel_support(struct nvhost_master *host)
+{
+	host->nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
+	host->nb_channels =  NVHOST_NUMCHANNELS;
+
+	host->op.channel.init = t20_channel_init;
+	host->op.channel.submit = host1x_channel_submit;
+	host->op.channel.read3dreg = host1x_channel_read_3d_reg;
+
+	return 0;
+}
+
 int nvhost_init_t20_support(struct nvhost_master *host)
 {
 	int err;
@@ -46,13 +202,13 @@ int nvhost_init_t20_support(struct nvhost_master *host)
 	err = nvhost_init_t20_channel_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_cdma_support(host);
+	err = host1x_init_cdma_support(host);
 	if (err)
 		return err;
 	err = nvhost_init_t20_debug_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_syncpt_support(host);
+	err = host1x_init_syncpt_support(host);
 	if (err)
 		return err;
 	err = nvhost_init_t20_intr_support(host);
@@ -63,94 +219,3 @@ int nvhost_init_t20_support(struct nvhost_master *host)
 		return err;
 	return 0;
 }
-
-int nvhost_t20_save_context(struct nvhost_module *mod, u32 syncpt_id)
-{
-	struct nvhost_channel *ch =
-			container_of(mod, struct nvhost_channel, mod);
-	struct nvhost_hwctx *hwctx_to_save;
-	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
-	u32 syncpt_incrs, syncpt_val;
-	int err = 0;
-	void *ref;
-	void *ctx_waiter = NULL, *wakeup_waiter = NULL;
-	struct nvhost_job *job;
-
-	ctx_waiter = nvhost_intr_alloc_waiter();
-	wakeup_waiter = nvhost_intr_alloc_waiter();
-	if (!ctx_waiter || !wakeup_waiter) {
-		err = -ENOMEM;
-		goto done;
-	}
-
-	if (mod->desc->busy)
-		mod->desc->busy(mod);
-
-	mutex_lock(&ch->submitlock);
-	hwctx_to_save = ch->cur_ctx;
-	if (!hwctx_to_save) {
-		mutex_unlock(&ch->submitlock);
-		goto done;
-	}
-
-	job = nvhost_job_alloc(ch, hwctx_to_save,
-			NULL,
-			ch->dev->nvmap, 0, 0);
-	if (IS_ERR_OR_NULL(job)) {
-		err = PTR_ERR(job);
-		mutex_unlock(&ch->submitlock);
-		goto done;
-	}
-
-	hwctx_to_save->valid = true;
-	ch->ctxhandler.get(hwctx_to_save);
-	ch->cur_ctx = NULL;
-
-	syncpt_incrs = hwctx_to_save->save_incrs;
-	syncpt_val = nvhost_syncpt_incr_max(&ch->dev->syncpt,
-					syncpt_id, syncpt_incrs);
-
-	job->syncpt_id = syncpt_id;
-	job->syncpt_incrs = syncpt_incrs;
-	job->syncpt_end = syncpt_val;
-
-	err = nvhost_cdma_begin(&ch->cdma, job);
-	if (err) {
-		mutex_unlock(&ch->submitlock);
-		goto done;
-	}
-
-	ch->ctxhandler.save_push(&ch->cdma, hwctx_to_save);
-	nvhost_cdma_end(&ch->cdma, job);
-	nvhost_job_put(job);
-	job = NULL;
-
-	err = nvhost_intr_add_action(&ch->dev->intr, syncpt_id,
-			syncpt_val - syncpt_incrs + hwctx_to_save->save_thresh,
-			NVHOST_INTR_ACTION_CTXSAVE, hwctx_to_save,
-			ctx_waiter,
-			NULL);
-	ctx_waiter = NULL;
-	WARN(err, "Failed to set context save interrupt");
-
-	err = nvhost_intr_add_action(&ch->dev->intr, syncpt_id, syncpt_val,
-			NVHOST_INTR_ACTION_WAKEUP, &wq,
-			wakeup_waiter,
-			&ref);
-	wakeup_waiter = NULL;
-	WARN(err, "Failed to set wakeup interrupt");
-	wait_event(wq,
-		nvhost_syncpt_min_cmp(&ch->dev->syncpt,
-				syncpt_id, syncpt_val));
-
-	nvhost_intr_put_ref(&ch->dev->intr, ref);
-
-	nvhost_cdma_update(&ch->cdma);
-
-	mutex_unlock(&ch->submitlock);
-
-done:
-	kfree(ctx_waiter);
-	kfree(wakeup_waiter);
-	return err;
-}
diff --git a/drivers/video/tegra/host/t20/t20.h b/drivers/video/tegra/host/t20/t20.h
index e7dd0a2a93ca..c7eac39ba089 100644
--- a/drivers/video/tegra/host/t20/t20.h
+++ b/drivers/video/tegra/host/t20/t20.h
@@ -26,7 +26,6 @@ struct nvhost_master;
 struct nvhost_module;
 
 int nvhost_init_t20_channel_support(struct nvhost_master *);
-int nvhost_init_t20_cdma_support(struct nvhost_master *);
 int nvhost_init_t20_debug_support(struct nvhost_master *);
 int nvhost_init_t20_syncpt_support(struct nvhost_master *);
 int nvhost_init_t20_intr_support(struct nvhost_master *);
diff --git a/drivers/video/tegra/host/t30/Makefile b/drivers/video/tegra/host/t30/Makefile
index ae6456656994..b343eb4fc7cc 100644
--- a/drivers/video/tegra/host/t30/Makefile
+++ b/drivers/video/tegra/host/t30/Makefile
@@ -1,8 +1,8 @@
 GCOV_PROFILE := y
 
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+
 nvhost-t30-objs  = \
-	t30.o \
-	channel_t30.o \
-	debug_t30.o
+	t30.o
 
 obj-$(CONFIG_TEGRA_GRHOST) += nvhost-t30.o
diff --git a/drivers/video/tegra/host/t30/channel_t30.c b/drivers/video/tegra/host/t30/channel_t30.c
deleted file mode 100644
index d2286bdd3231..000000000000
--- a/drivers/video/tegra/host/t30/channel_t30.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * drivers/video/tegra/host/t30/channel_t30.c
- *
- * Tegra Graphics Host Channel
- *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/mutex.h>
-#include <mach/powergate.h>
-
-#include "../gr3d/gr3d_t30.h"
-#include "../gr3d/scale3d.h"
-
-#include "../dev.h"
-#include "../t20/channel_t20.h"
-#include "../t20/t20.h"
-#include "../t20/syncpt_t20.h"
-#include "../gr3d/gr3d.h"
-#include "../mpe/mpe.h"
-
-#define NVMODMUTEX_2D_FULL   (1)
-#define NVMODMUTEX_2D_SIMPLE (2)
-#define NVMODMUTEX_2D_SB_A   (3)
-#define NVMODMUTEX_2D_SB_B   (4)
-#define NVMODMUTEX_3D        (5)
-#define NVMODMUTEX_DISPLAYA  (6)
-#define NVMODMUTEX_DISPLAYB  (7)
-#define NVMODMUTEX_VI        (8)
-#define NVMODMUTEX_DSI       (9)
-
-#ifndef TEGRA_POWERGATE_3D1
-#define TEGRA_POWERGATE_3D1 -1
-#endif
-
-const struct nvhost_channeldesc nvhost_t30_channelmap[] = {
-{
-	/* channel 0 */
-	.name	       = "display",
-	.syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
-			 BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
-			 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
-			 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
-	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 1 */
-	.name	       = "gr3d",
-	.syncpts       = BIT(NVSYNCPT_3D),
-	.waitbases     = BIT(NVWAITBASE_3D),
-	.modulemutexes = BIT(NVMODMUTEX_3D),
-	.class	       = NV_GRAPHICS_3D_CLASS_ID,
-	.module        = {
-			.prepare_poweroff = nvhost_gr3d_prepare_power_off,
-			.busy = nvhost_scale3d_notify_busy,
-			.idle = nvhost_scale3d_notify_idle,
-			.init = nvhost_scale3d_init,
-			.deinit = nvhost_scale3d_deinit,
-			.suspend = nvhost_scale3d_suspend,
-			.clocks = {{"gr3d", UINT_MAX},
-					{"gr3d2", UINT_MAX},
-					{"emc", UINT_MAX} },
-			.powergate_ids = {TEGRA_POWERGATE_3D,
-					TEGRA_POWERGATE_3D1},
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			.can_powergate = true,
-			.powergate_delay = 100,
-	},
-},
-{
-	/* channel 2 */
-	.name	       = "gr2d",
-	.syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-	.waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
-	.module        = {
-			.clocks = {{"gr2d", 0},
-					{"epp", 0},
-					{"emc", 300000000} },
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			.clockgate_delay = 0,
-			},
-},
-{
-	/* channel 3 */
-	.name	 = "isp",
-	.syncpts = 0,
-	.module         = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 4 */
-	.name	       = "vi",
-	.syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-			 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-			 BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-			 BIT(NVSYNCPT_VI_ISP_4),
-	.modulemutexes = BIT(NVMODMUTEX_VI),
-	.exclusive     = true,
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			},
-},
-{
-	/* channel 5 */
-	.name	       = "mpe",
-	.syncpts       = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
-			 BIT(NVSYNCPT_MPE_WR_SAFE),
-	.waitbases     = BIT(NVWAITBASE_MPE),
-	.class	       = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
-	.waitbasesync  = true,
-	.keepalive     = true,
-	.module        = {
-			.prepare_poweroff = nvhost_mpe_prepare_power_off,
-			.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
-			.powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-			.can_powergate  = true,
-			.powergate_delay = 100,
-			},
-},
-{
-	/* channel 6 */
-	.name	       = "dsi",
-	.syncpts       = BIT(NVSYNCPT_DSI),
-	.modulemutexes = BIT(NVMODMUTEX_DSI),
-	.module        = {
-			NVHOST_MODULE_NO_POWERGATE_IDS,
-			NVHOST_DEFAULT_CLOCKGATE_DELAY,
-	},
-} };
-
-#define NVHOST_CHANNEL_BASE 0
-
-static inline int t30_nvhost_hwctx_handler_init(
-	struct nvhost_hwctx_handler *h,
-	const char *module)
-{
-	if (strcmp(module, "gr3d") == 0)
-		return nvhost_gr3d_t30_ctxhandler_init(h);
-	else if (strcmp(module, "mpe") == 0)
-		return nvhost_mpe_ctxhandler_init(h);
-
-	return 0;
-}
-
-static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx)
-{
-	ndx += NVHOST_CHANNEL_BASE;
-	p += NV_HOST1X_CHANNEL0_BASE;
-	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
-	return p;
-}
-
-static int t30_channel_init(struct nvhost_channel *ch,
-			    struct nvhost_master *dev, int index)
-{
-	ch->dev = dev;
-	ch->chid = index;
-	ch->desc = nvhost_t30_channelmap + index;
-	mutex_init(&ch->reflock);
-	mutex_init(&ch->submitlock);
-
-	ch->aperture = t30_channel_aperture(dev->aperture, index);
-
-	return t30_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->desc->name);
-}
-
-int nvhost_init_t30_channel_support(struct nvhost_master *host)
-{
-	int result = nvhost_init_t20_channel_support(host);
-	host->op.channel.init = t30_channel_init;
-
-	return result;
-}
diff --git a/drivers/video/tegra/host/t30/debug_t30.c b/drivers/video/tegra/host/t30/debug_t30.c
deleted file mode 100644
index 5d4066df6ce9..000000000000
--- a/drivers/video/tegra/host/t30/debug_t30.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * drivers/video/tegra/host/t30/debug_t30.c
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "../dev.h"
-#include "../gr3d/scale3d.h"
-#include "../t20/t20.h"
-#include "../chip_support.h"
-
-int nvhost_init_t30_debug_support(struct nvhost_master *host)
-{
-	nvhost_init_t20_debug_support(host);
-	host->op.debug.debug_init = nvhost_scale3d_debug_init;
-
-	return 0;
-}
diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c
index 265b0fe5c7e0..425b352a66a8 100644
--- a/drivers/video/tegra/host/t30/t30.c
+++ b/drivers/video/tegra/host/t30/t30.c
@@ -20,8 +20,19 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#include "../dev.h"
+#include <linux/mutex.h>
+#include <mach/powergate.h>
+#include "dev.h"
 #include "t30.h"
+#include "gr3d/gr3d.h"
+#include "mpe/mpe.h"
+#include "gr3d/gr3d_t30.h"
+#include "gr3d/scale3d.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_cdma.h"
+#include "host1x/host1x_syncpt.h"
+#include "gr3d/scale3d.h"
+#include "../chip_support.h"
 
 static struct nvhost_device devices[] = {
 	{.name   = "gr3d", .id = -1 },
@@ -32,6 +43,176 @@ static struct nvhost_device devices[] = {
 	{.name = "dsi", .id = -1 },
 };
 
+#define NVMODMUTEX_2D_FULL   (1)
+#define NVMODMUTEX_2D_SIMPLE (2)
+#define NVMODMUTEX_2D_SB_A   (3)
+#define NVMODMUTEX_2D_SB_B   (4)
+#define NVMODMUTEX_3D        (5)
+#define NVMODMUTEX_DISPLAYA  (6)
+#define NVMODMUTEX_DISPLAYB  (7)
+#define NVMODMUTEX_VI        (8)
+#define NVMODMUTEX_DSI       (9)
+
+#ifndef TEGRA_POWERGATE_3D1
+#define TEGRA_POWERGATE_3D1 -1
+#endif
+
+const struct nvhost_channeldesc nvhost_t30_channelmap[] = {
+{
+	/* channel 0 */
+	.name	       = "display",
+	.syncpts       = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
+			 BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
+			 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
+			 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
+	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 1 */
+	.name	       = "gr3d",
+	.syncpts       = BIT(NVSYNCPT_3D),
+	.waitbases     = BIT(NVWAITBASE_3D),
+	.modulemutexes = BIT(NVMODMUTEX_3D),
+	.class	       = NV_GRAPHICS_3D_CLASS_ID,
+	.module        = {
+			.prepare_poweroff = nvhost_gr3d_prepare_power_off,
+			.busy = nvhost_scale3d_notify_busy,
+			.idle = nvhost_scale3d_notify_idle,
+			.init = nvhost_scale3d_init,
+			.deinit = nvhost_scale3d_deinit,
+			.suspend = nvhost_scale3d_suspend,
+			.clocks = {{"gr3d", UINT_MAX},
+					{"gr3d2", UINT_MAX},
+					{"emc", UINT_MAX} },
+			.powergate_ids = {TEGRA_POWERGATE_3D,
+					TEGRA_POWERGATE_3D1},
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			.can_powergate = true,
+			.powergate_delay = 100,
+	},
+},
+{
+	/* channel 2 */
+	.name	       = "gr2d",
+	.syncpts       = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+	.waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
+	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
+			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+	.module        = {
+			.clocks = {{"gr2d", 0},
+					{"epp", 0},
+					{"emc", 300000000} },
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			.clockgate_delay = 0,
+			},
+},
+{
+	/* channel 3 */
+	.name	 = "isp",
+	.syncpts = 0,
+	.module         = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 4 */
+	.name	       = "vi",
+	.syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
+			 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
+			 BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
+			 BIT(NVSYNCPT_VI_ISP_4),
+	.modulemutexes = BIT(NVMODMUTEX_VI),
+	.exclusive     = true,
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			},
+},
+{
+	/* channel 5 */
+	.name	       = "mpe",
+	.syncpts       = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
+			 BIT(NVSYNCPT_MPE_WR_SAFE),
+	.waitbases     = BIT(NVWAITBASE_MPE),
+	.class	       = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+	.waitbasesync  = true,
+	.keepalive     = true,
+	.module        = {
+			.prepare_poweroff = nvhost_mpe_prepare_power_off,
+			.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
+			.powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+			.can_powergate  = true,
+			.powergate_delay = 100,
+			},
+},
+{
+	/* channel 6 */
+	.name	       = "dsi",
+	.syncpts       = BIT(NVSYNCPT_DSI),
+	.modulemutexes = BIT(NVMODMUTEX_DSI),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATE_IDS,
+			NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	},
+} };
+
+#define NVHOST_CHANNEL_BASE 0
+
+static inline int t30_nvhost_hwctx_handler_init(
+	struct nvhost_hwctx_handler *h,
+	const char *module)
+{
+	if (strcmp(module, "gr3d") == 0)
+		return nvhost_gr3d_t30_ctxhandler_init(h);
+	else if (strcmp(module, "mpe") == 0)
+		return nvhost_mpe_ctxhandler_init(h);
+
+	return 0;
+}
+
+static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx)
+{
+	ndx += NVHOST_CHANNEL_BASE;
+	p += NV_HOST1X_CHANNEL0_BASE;
+	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
+	return p;
+}
+
+static int t30_channel_init(struct nvhost_channel *ch,
+			    struct nvhost_master *dev, int index)
+{
+	ch->dev = dev;
+	ch->chid = index;
+	ch->desc = nvhost_t30_channelmap + index;
+	mutex_init(&ch->reflock);
+	mutex_init(&ch->submitlock);
+
+	ch->aperture = t30_channel_aperture(dev->aperture, index);
+
+	return t30_nvhost_hwctx_handler_init(&ch->ctxhandler, ch->desc->name);
+}
+
+int nvhost_init_t30_channel_support(struct nvhost_master *host)
+{
+	int result = nvhost_init_t20_channel_support(host);
+	host->op.channel.init = t30_channel_init;
+
+	return result;
+}
+int nvhost_init_t30_debug_support(struct nvhost_master *host)
+{
+	nvhost_init_t20_debug_support(host);
+	host->op.debug.debug_init = nvhost_scale3d_debug_init;
+
+	return 0;
+}
+
 int nvhost_init_t30_support(struct nvhost_master *host)
 {
 	int err;
@@ -44,13 +225,13 @@ int nvhost_init_t30_support(struct nvhost_master *host)
 	err = nvhost_init_t30_channel_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_cdma_support(host);
+	err = host1x_init_cdma_support(host);
 	if (err)
 		return err;
 	err = nvhost_init_t30_debug_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_syncpt_support(host);
+	err = host1x_init_syncpt_support(host);
 	if (err)
 		return err;
 	err = nvhost_init_t20_intr_support(host);