diff options
| author | Nitin Kumbhar <nkumbhar@nvidia.com> | 2012-01-27 11:13:21 +0530 |
|---|---|---|
| committer | Lokesh Pathak <lpathak@nvidia.com> | 2012-02-23 05:19:27 -0800 |
| commit | d9ecb9be27bb10535159ebb43ca3fa515edfc13b (patch) | |
| tree | 137c3ddebcc1a35d250f8a83d64184c428be2cad /drivers/video | |
| parent | dc0d386089f96026ba60b75695ca64fd2e58ac80 (diff) | |
video: tegra: dc: in continuous mode mask VBLANK after first frame
A V_BLANK interrupt for each frame does not allow long lp2 idle intervals.
If all windows are clean, mask V_BLANK interrupt after processing it
for updating smart dimmer. It's unmasked again when a new window update
is performed. This will schedule a work for updating smart dimmer for
the new frame.
Bug 920110
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85137
(cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6)
Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85166
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index e64b935e4c12..2ee5860f0f91 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -2090,6 +2090,18 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc) } #ifndef CONFIG_TEGRA_FPGA_PLATFORM +static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc) +{ +#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM + u32 val; + + val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); + if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE)) + return true; +#endif + return false; +} + static void tegra_dc_trigger_windows(struct tegra_dc *dc) { u32 val, i; @@ -2157,6 +2169,15 @@ static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status) if (status & V_BLANK_INT) { /* Schedule any additional bottom-half vblank actvities. */ schedule_work(&dc->vblank_work); + + /* All windows updated. Mask subsequent V_BLANK interrupts */ + if (!tegra_dc_windows_are_dirty(dc)) { + u32 val; + + val = tegra_dc_readl(dc, DC_CMD_INT_MASK); + val &= ~V_BLANK_INT; + tegra_dc_writel(dc, val, DC_CMD_INT_MASK); + } } if (status & FRAME_END_INT) { |