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authorJoseph Lehrer <jlehrer@nvidia.com>2011-02-13 17:29:36 -0800
committerVarun Colbert <vcolbert@nvidia.com>2011-02-22 18:27:55 -0800
commit8848cbcacee9065d65413f19150bcb4e919b82fb (patch)
tree619b92efca2a69bb5bc352b956e026c1159ec8f4 /drivers
parenta18784e6928701cce8623f0dba1dde4900ab909a (diff)
tegra: dc: Add PMx PWM control
bug 773671 Change-Id: If4265051873809491c80ada9401e48014c15f63d Reviewed-on: http://git-master/r/19397 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/tegra/dc/dc.c25
-rw-r--r--drivers/video/tegra/dc/dc_reg.h4
2 files changed, 29 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index f8159331877a..fe6150f6aabf 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -813,6 +813,31 @@ int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
}
EXPORT_SYMBOL(tegra_dc_set_mode);
+void
+tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
+{
+ unsigned int ctrl;
+
+ ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
+ (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
+ cfg->clk_select);
+
+ switch (cfg->which_pwm) {
+ case TEGRA_PWM_PM0:
+ tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
+ tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
+ break;
+ case TEGRA_PWM_PM1:
+ tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
+ tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
+ break;
+ default:
+ dev_err(&dc->ndev->dev, "Error\n");
+ return;
+ }
+}
+EXPORT_SYMBOL(tegra_dc_config_pwm);
+
static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
const struct tegra_dc_out_pin *pins,
const unsigned int n_pins)
diff --git a/drivers/video/tegra/dc/dc_reg.h b/drivers/video/tegra/dc/dc_reg.h
index 240d8a48d03e..1bb2b00f6c71 100644
--- a/drivers/video/tegra/dc/dc_reg.h
+++ b/drivers/video/tegra/dc/dc_reg.h
@@ -145,6 +145,10 @@
#define DC_COM_PM0_DUTY_CYCLE 0x31d
#define DC_COM_PM1_CONTROL 0x31e
#define DC_COM_PM1_DUTY_CYCLE 0x31f
+
+#define PM_PERIOD_SHIFT 18
+#define PM_CLK_DIVIDER_SHIFT 4
+
#define DC_COM_SPI_CONTROL 0x320
#define DC_COM_SPI_START_BYTE 0x321
#define DC_COM_HSPI_WRITE_DATA_AB 0x322