Merge remote branch 'fsl-linux-sdk/imx_3.0.15_12.04.01' into imx_3.0.15_android

Conflicts:
	arch/arm/kernel/traps.c
	arch/arm/mach-mx6/board-mx6q_sabresd.c
	arch/arm/mach-mx6/cpu.c
	arch/arm/mach-mx6/system.c

23 files changed, 2098 insertions, 85 deletions

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 6f168fe568a8..b6c7211ccd52 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -576,6 +576,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
 		emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 		break;
 	case IMX_DMATYPE_SSI_SP:
+		per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
+		emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
+		break;
 	case IMX_DMATYPE_MMC:
 	case IMX_DMATYPE_SDHC:
 	case IMX_DMATYPE_CSPI_SP:
@@ -1125,6 +1128,7 @@ static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
 			sdmac->word_size = dmaengine_cfg->dst_addr_width;
 		}
+		sdmac->direction = dmaengine_cfg->direction;
 		return sdma_config_channel(sdmac);
 	default:
 		return -ENOSYS;
@@ -1155,7 +1159,7 @@ static void sdma_issue_pending(struct dma_chan *chan)
 	 */
 }
 
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	37
 
 static void sdma_add_scripts(struct sdma_engine *sdma,
 		const struct sdma_script_start_addrs *addr)
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 4456b331e1d5..162e6c3eb64d 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -637,7 +637,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
 		goto err_ioremap;
 	}
 
-	mxs_dma->clk = clk_get(&pdev->dev, NULL);
+	mxs_dma->clk = clk_get(NULL, "mxs-dma-apbh");
 	if (IS_ERR(mxs_dma->clk)) {
 		ret = PTR_ERR(mxs_dma->clk);
 		goto err_clk;
diff --git a/drivers/media/radio/Kconfig b/drivers/media/radio/Kconfig
index 52798a111e16..4aefb00cc6cf 100644
--- a/drivers/media/radio/Kconfig
+++ b/drivers/media/radio/Kconfig
@@ -355,6 +355,19 @@ config RADIO_SI470X
 	bool "Silicon Labs Si470x FM Radio Receiver support"
 	depends on VIDEO_V4L2
 
+config I2C_SI4763
+	tristate "Silicon Labs Si4763 AMFM Radio Transmitter support"
+	depends on I2C && VIDEO_V4L2
+	---help---
+	  Say Y here if you want support to Si4763 AMFM Radio Transmitter.
+	  This device can transmit audio through AM or FM.
+	  This module is the v4l2 radio
+	  interface for the i2c driver of this device.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called radio-si4763.
+
+
 source "drivers/media/radio/si470x/Kconfig"
 
 config USB_MR800
diff --git a/drivers/media/radio/Makefile b/drivers/media/radio/Makefile
index f484a6e04eb2..07cd9ef0e19a 100644
--- a/drivers/media/radio/Makefile
+++ b/drivers/media/radio/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RADIO_ZOLTRIX) += radio-zoltrix.o
 obj-$(CONFIG_RADIO_GEMTEK) += radio-gemtek.o
 obj-$(CONFIG_RADIO_TRUST) += radio-trust.o
 obj-$(CONFIG_I2C_SI4713) += si4713-i2c.o
+obj-$(CONFIG_I2C_SI4763) += si4763-i2c.o
 obj-$(CONFIG_RADIO_SI4713) += radio-si4713.o
 obj-$(CONFIG_RADIO_MIROPCM20) += radio-miropcm20.o
 obj-$(CONFIG_USB_DSBR) += dsbr100.o
diff --git a/drivers/media/radio/si4763-i2c.c b/drivers/media/radio/si4763-i2c.c
new file mode 100644
index 000000000000..c4990a3eee5d
--- /dev/null
+++ b/drivers/media/radio/si4763-i2c.c
@@ -0,0 +1,933 @@
+/*
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-common.h>
+
+#include "si4763-i2c.h"
+
+#define DEBUG 1
+/* module parameters */
+static int debug;
+module_param(debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(debug, "Debug level (0 - 2)");
+
+MODULE_DESCRIPTION("I2C driver for Si4763 FM Radio Transmitter");
+
+/* Radio Nr */
+static int radio_nr = -1;
+
+
+/* radio_si4713_fops - file operations interface */
+static const struct v4l2_file_operations radio_si4763_fops = {
+	.owner          = THIS_MODULE,
+	.ioctl          = video_ioctl2,
+};
+
+
+#define DEFAULT_RDS_PI			0x00
+#define DEFAULT_RDS_PTY			0x00
+#define DEFAULT_RDS_PS_NAME		""
+#define DEFAULT_RDS_RADIO_TEXT		DEFAULT_RDS_PS_NAME
+#define DEFAULT_RDS_DEVIATION		0x00C8
+#define DEFAULT_RDS_PS_REPEAT_COUNT	0x0003
+#define DEFAULT_LIMITER_RTIME		0x1392
+#define DEFAULT_LIMITER_DEV		0x102CA
+#define DEFAULT_PILOT_FREQUENCY	0x4A38
+#define DEFAULT_PILOT_DEVIATION		0x1A5E
+#define DEFAULT_ACOMP_ATIME		0x0000
+#define DEFAULT_ACOMP_RTIME		0xF4240L
+#define DEFAULT_ACOMP_GAIN		0x0F
+#define DEFAULT_ACOMP_THRESHOLD	(-0x28)
+#define DEFAULT_MUTE			0x01
+#define DEFAULT_POWER_LEVEL		88
+#define DEFAULT_FREQUENCY		8800
+#define DEFAULT_PREEMPHASIS		FMPE_EU
+#define DEFAULT_TUNE_RNL		0xFF
+
+#define to_si4763_device(sd)	container_of(sd, struct si4763_device, sd)
+
+/* frequency domain transformation (using times 10 to avoid floats) */
+#define FREQ_RANGE_LOW			8750
+#define FREQ_RANGE_HIGH			10800
+
+#define MAX_ARGS 7
+
+#define RDS_BLOCK			8
+#define RDS_BLOCK_CLEAR			0x03
+#define RDS_BLOCK_LOAD			0x04
+#define RDS_RADIOTEXT_2A		0x20
+#define RDS_RADIOTEXT_BLK_SIZE		4
+#define RDS_RADIOTEXT_INDEX_MAX		0x0F
+#define RDS_CARRIAGE_RETURN		0x0D
+
+#define rds_ps_nblocks(len)	((len / RDS_BLOCK) + (len % RDS_BLOCK ? 1 : 0))
+
+#define get_status_bit(p, b, m)	(((p) & (m)) >> (b))
+#define set_bits(p, v, b, m)	(((p) & ~(m)) | ((v) << (b)))
+
+#define ATTACK_TIME_UNIT	500
+
+#define POWER_OFF			0x00
+#define POWER_ON			0x01
+
+#define msb(x)                  ((u8)((u16) x >> 8))
+#define lsb(x)                  ((u8)((u16) x &  0x00FF))
+#define compose_u16(msb, lsb)	(((u16)msb << 8) | lsb)
+#define compose_u32(msb, lsb)   (((u32)msb << 16) | lsb)
+#define check_command_failed(status)	(!(status & SI4713_CTS) || \
+					(status & SI4713_ERR))
+/* mute definition */
+#define set_mute(p)	((p & 1) | ((p & 1) << 1));
+#define get_mute(p)	(p & 0x01)
+
+#ifdef DEBUG
+#define DBG_BUFFER(device, message, buffer, size)			\
+	{								\
+		int i;							\
+		char str[(size)*5];					\
+		for (i = 0; i < size; i++)				\
+			sprintf(str + i * 5, " 0x%02x", buffer[i]);	\
+		v4l2_dbg(2, debug, device, "%s:%s\n", message, str);	\
+	}
+#else
+#define DBG_BUFFER(device, message, buffer, size)
+#endif
+
+
+/*
+ * si4713_send_command - sends a command to si4713 and waits its response
+ * @sdev: si4713_device structure for the device we are communicating
+ * @command: command id
+ * @args: command arguments we are sending (up to 7)
+ * @argn: actual size of @args
+ * @response: buffer to place the expected response from the device (up to 15)
+ * @respn: actual size of @response
+ * @usecs: amount of time to wait before reading the response (in usecs)
+ */
+static int si4713_send_command(struct si4763_device *sdev, const u8 command,
+				const u8 args[], const int argn,
+				u8 response[], const int respn, const int usecs)
+{
+	struct i2c_client *client = sdev->client;
+	u8 data1[MAX_ARGS + 1];
+	int err;
+	int i;
+	if (!client->adapter)
+		return -ENODEV;
+
+	/* First send the command and its arguments */
+	data1[0] = command;
+	memcpy(data1 + 1, args, argn);
+	DBG_BUFFER(&sdev->sd, "Parameters", data1, argn + 1);
+
+	err = i2c_master_send(client, data1, argn + 1);
+	if (err != argn + 1) {
+		v4l2_err(&sdev->sd, "Error while sending command 0x%02x\n",
+			command);
+		return (err > 0) ? -EIO : err;
+	}
+
+	/* Wait response from interrupt */
+/*
+	if (!wait_for_completion_timeout(&sdev->work,
+				usecs_to_jiffies(usecs) + 1))
+		v4l2_warn(&sdev->sd,
+				"(%s) Device took too much time to answer.\n",
+				__func__);
+
+*/
+
+
+	/* Then get the response */
+	i = 0;
+	err = i2c_master_recv(client, response, respn);
+	while (i++ < usecs && ((response[0] & 0x80) != 0x80)) {
+		err = i2c_master_recv(client, response, respn);
+		udelay(1);
+	}
+
+
+	if (err != respn) {
+		v4l2_err(&sdev->sd,
+			"Error while reading response for command 0x%02x\n",
+			command);
+		return (err > 0) ? -EIO : err;
+	}
+
+	DBG_BUFFER(&sdev->sd, "Response", response, respn);
+	if (check_command_failed(response[0]))
+		return -EBUSY;
+
+	return 0;
+}
+
+
+/*
+ * si4713_write_property - modifies a si4713 property
+ * @sdev: si4713_device structure for the device we are communicating
+ * @prop: property identification number
+ * @val: new value for that property
+ */
+static int si4713_write_property(struct si4763_device *sdev, u16 prop, u16 val)
+{
+	int rval;
+	u8 resp[SI4713_SET_PROP_NRESP];
+	/*
+	*	.First byte = 0
+	*	.Second byte = property's MSB
+	*	.Third byte = property's LSB
+	*	.Fourth byte = value's MSB
+	*	.Fifth byte = value's LSB
+	*/
+	const u8 args[SI4713_SET_PROP_NARGS] = {
+		0x00,
+		msb(prop),
+		lsb(prop),
+		msb(val),
+		lsb(val),
+	};
+
+	rval = si4713_send_command(sdev, SI4713_CMD_SET_PROPERTY,
+					args, ARRAY_SIZE(args),
+					resp, ARRAY_SIZE(resp),
+					DEFAULT_TIMEOUT);
+
+	if (rval < 0)
+		return rval;
+
+	v4l2_dbg(1, debug, &sdev->sd,
+			"%s: property=0x%02x value=0x%02x status=0x%02x\n",
+			__func__, prop, val, resp[0]);
+
+	/*
+	 * As there is no command response for SET_PROPERTY,
+	 * wait Tcomp time to finish before proceed, in order
+	 * to have property properly set.
+	 */
+	msleep(TIMEOUT_SET_PROPERTY);
+
+	return rval;
+}
+
+static int si4713_enable_digitalout(struct si4763_device *sdev)
+{
+	int rval;
+	u8 resp[SI4713_SET_PROP_NRESP];
+	/*
+	*      .First byte = 0
+	*      .Second byte = property's MSB
+	*      .Third byte = property's LSB
+	*      .Fourth byte = value's MSB
+	*      .Fifth byte = value's LSB
+	*/
+	const u8 args[SI4713_EN_DIGITALOUT_NARGS] = {
+		10,
+		10,
+		12,
+		0,
+	};
+
+	rval = si4713_send_command(sdev, SI4713_CMD_EN_DIGITALOUT,
+		args, ARRAY_SIZE(args),
+		resp, ARRAY_SIZE(resp),
+		DEFAULT_TIMEOUT);
+
+	if (rval < 0)
+		return rval;
+
+
+	/*
+	* As there is no command response for SET_PROPERTY,
+	* wait Tcomp time to finish before proceed, in order
+	 * to have property properly set.
+	*/
+	msleep(TIMEOUT_SET_PROPERTY);
+
+	return rval;
+}
+
+static int si4713_get_digitalout(struct si4763_device *sdev, u32 *response)
+{
+	int rval;
+	u8 resp[5];
+	u16 temp1, temp2;
+
+	/*
+	 *      .First byte = 0
+	*      .Second byte = property's MSB
+	 *      .Third byte = property's LSB
+	*      .Fourth byte = value's MSB
+	*      .Fifth byte = value's LSB
+	*/
+	const u8 args[SI4713_EN_DIGITALOUT_NARGS] = {
+		0,
+		0,
+		0,
+		0,
+	};
+
+	rval = si4713_send_command(sdev, SI4713_CMD_EN_DIGITALOUT,
+		args, ARRAY_SIZE(args),
+		resp, ARRAY_SIZE(resp),
+		DEFAULT_TIMEOUT);
+
+	if (rval < 0)
+		return rval;
+
+	temp1 = compose_u16(resp[1], resp[2]);
+	temp2 = compose_u16(resp[3], resp[4]);
+	*response = compose_u32(temp1, temp2);
+	/*
+	* As there is no command response for SET_PROPERTY,
+	* wait Tcomp time to finish before proceed, in order
+	* to have property properly set.
+	*/
+	msleep(TIMEOUT_SET_PROPERTY);
+
+	return rval;
+}
+
+
+/*
+ * si4713_powerup - Powers the device up
+ * @sdev: si4713_device structure for the device we are communicating
+ */
+static int si4713_powerup(struct si4763_device *sdev)
+{
+	int err;
+	u8 resp[SI4760_PWUP_NRESP];
+	const u8 args[SI4760_PWUP_NARGS] = {
+		SI4760_PWUP_ARG1,
+		SI4760_PWUP_ARG2,
+		SI4760_PWUP_ARG3,
+		SI4760_PWUP_ARG4,
+		SI4760_PWUP_ARG5,
+	};
+
+
+	if (sdev->power_state)
+		return 0;
+	err = si4713_send_command(sdev, SI4760_CMD_POWER_UP,
+					args, ARRAY_SIZE(args),
+					resp, ARRAY_SIZE(resp),
+					TIMEOUT_POWER_UP);
+
+	if (!err) {
+		v4l2_dbg(1, debug, &sdev->sd, "Powerup response: 0x%02x\n",
+				resp[0]);
+		v4l2_dbg(1, debug, &sdev->sd, "Device in power up mode\n");
+		sdev->power_state = POWER_ON;
+
+	} else {
+	/*	if (gpio_is_valid(sdev->gpio_reset))
+			gpio_set_value(sdev->gpio_reset, 0);
+		err = regulator_bulk_disable(ARRAY_SIZE(sdev->supplies),
+						     sdev->supplies);
+	*/	if (err)
+			v4l2_err(&sdev->sd,
+				 "Failed to disable supplies: %d\n", err);
+	}
+
+	return err;
+}
+
+/*
+ * si4713_powerdown - Powers the device down
+ * @sdev: si4713_device structure for the device we are communicating
+ */
+static int si4713_powerdown(struct si4763_device *sdev)
+{
+	int err;
+	u8 resp[SI4760_PWDN_NRESP];
+
+
+	err = si4713_send_command(sdev, SI4760_CMD_POWER_DOWN,
+					NULL, 0,
+					resp, ARRAY_SIZE(resp),
+					DEFAULT_TIMEOUT);
+
+	if (!err) {
+		v4l2_dbg(1, debug, &sdev->sd, "Power down response: 0x%02x\n",
+				resp[0]);
+		v4l2_dbg(1, debug, &sdev->sd, "Device in reset mode\n");
+		if (err)
+			v4l2_err(&sdev->sd,
+				 "Failed to disable supplies: %d\n", err);
+		sdev->power_state = POWER_OFF;
+	}
+
+	return err;
+}
+
+/*
+ * si4713_checkrev - Checks if we are treating a device with the correct rev.
+ * @sdev: si4713_device structure for the device we are communicating
+ */
+static int si4713_checkrev(struct si4763_device *sdev)
+{
+	struct i2c_client *client = sdev->client;
+	int rval;
+	u8 resp[SI4760_GETREV_NRESP];
+
+	mutex_lock(&sdev->mutex);
+
+	rval = si4713_send_command(sdev, SI4760_CMD_GET_REV,
+					NULL, 0,
+					resp, ARRAY_SIZE(resp),
+					DEFAULT_TIMEOUT);
+
+	if (rval < 0)
+		goto unlock;
+
+	if (resp[1] == SI4760_PRODUCT_NUMBER) {
+		v4l2_info(&sdev->sd, "chip found @ 0x%02x (%s)\n",
+				client->addr << 1, client->adapter->name);
+	} else {
+		v4l2_err(&sdev->sd, "Invalid product number\n");
+		rval = -EINVAL;
+	}
+
+unlock:
+	mutex_unlock(&sdev->mutex);
+	return rval;
+}
+
+/*
+ * si4713_wait_stc - Waits STC interrupt and clears status bits. Usefull
+ *		     for TX_TUNE_POWER, TX_TUNE_FREQ and TX_TUNE_MEAS
+ * @sdev: si4713_device structure for the device we are communicating
+ * @usecs: timeout to wait for STC interrupt signal
+ */
+static int si4713_wait_stc(struct si4763_device *sdev, const int usecs)
+{
+	int err;
+	u8 resp[SI4713_GET_STATUS_NRESP];
+
+	/* Wait response from STC interrupt */
+	if (!wait_for_completion_timeout(&sdev->work,
+			usecs_to_jiffies(usecs) + 1))
+		v4l2_warn(&sdev->sd,
+			"%s: device took too much time to answer (%d usec).\n",
+				__func__, usecs);
+
+	/* Clear status bits */
+	err = si4713_send_command(sdev, SI4713_CMD_GET_INT_STATUS,
+					NULL, 0,
+					resp, ARRAY_SIZE(resp),
+					DEFAULT_TIMEOUT);
+
+	if (err < 0)
+		goto exit;
+
+	v4l2_dbg(1, debug, &sdev->sd,
+			"%s: status bits: 0x%02x\n", __func__, resp[0]);
+
+	if (!(resp[0] & SI4713_STC_INT))
+		err = -EIO;
+
+exit:
+	return err;
+}
+
+/*
+ * si4713_tx_tune_freq - Sets the state of the RF carrier and sets the tuning
+ *			frequency between 76 and 108 MHz in 10 kHz units and
+ *			steps of 50 kHz.
+ * @sdev: si4713_device structure for the device we are communicating
+ * @frequency: desired frequency (76 - 108 MHz, unit 10 KHz, step 50 kHz)
+ */
+static int si4713_tx_tune_freq(struct si4763_device *sdev, u16 frequency)
+{
+	int err;
+	u8 val[SI4713_TXFREQ_NRESP];
+	/*
+	*	.First byte = 0
+	*	.Second byte = frequency's MSB
+	*	.Third byte = frequency's LSB
+	 */
+	const u8 args[SI4713_TXFREQ_NARGS] = {
+		0x00,
+		msb(frequency),
+		lsb(frequency),
+		0x00,
+		0x00,
+	};
+
+	err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_FREQ,
+				  args, ARRAY_SIZE(args), val,
+				  ARRAY_SIZE(val), DEFAULT_TIMEOUT);
+
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+
+/*
+ * si4713_tx_tune_measure - Enters receive mode and measures the received noise
+ *			level in units of dBuV on the selected frequency.
+ *			The Frequency must be between 76 and 108 MHz in 10 kHz
+ *			units and steps of 50 kHz. The command also sets the
+ *			antenna	tuning capacitance. A value of 0 means
+ *			autotuning, and a value of 1 to 191 indicates manual
+ *			override.
+ * @sdev: si4713_device structure for the device we are communicating
+ * @frequency: desired frequency (76 - 108 MHz, unit 10 KHz, step 50 kHz)
+ * @antcap: value of antenna tuning capacitor (0 - 191)
+ */
+static int si4713_tx_tune_measure(struct si4763_device *sdev, u16 frequency,
+					u8 antcap)
+{
+	int err;
+	u8 val[SI4713_TXMEA_NRESP];
+	/*
+	*	.First byte = 0
+	*	.Second byte = frequency's MSB
+	*	.Third byte = frequency's LSB
+	*	.Fourth byte = antcap
+	 */
+	const u8 args[SI4713_TXMEA_NARGS] = {
+		0x00,
+		msb(frequency),
+		lsb(frequency),
+		antcap,
+	};
+
+	sdev->tune_rnl = DEFAULT_TUNE_RNL;
+
+	if (antcap > SI4713_MAX_ANTCAP)
+		return -EDOM;
+
+	err = si4713_send_command(sdev, SI4713_CMD_TX_TUNE_MEASURE,
+				  args, ARRAY_SIZE(args), val,
+				  ARRAY_SIZE(val), DEFAULT_TIMEOUT);
+
+	if (err < 0)
+		return err;
+
+	v4l2_dbg(1, debug, &sdev->sd,
+			"%s: frequency=0x%02x antcap=0x%02x status=0x%02x\n",
+			__func__, frequency, antcap, val[0]);
+
+	return si4713_wait_stc(sdev, TIMEOUT_TX_TUNE);
+}
+
+static int si4763_fm_rsq_status(struct si4763_device *sdev,
+					u16 *frequency)
+{
+	int err;
+	u8 val[SI4763_FM_RSQ_STATUS_NRESP];
+	/*
+	*	.First byte = intack bit
+	 */
+	const u8 args[SI4763_FM_RSQ_STATUS_NARGS] = {
+		0x00,
+	};
+
+	err = si4713_send_command(sdev, SI4763_CMD_FM_RSQ_STATUS,
+				  args, ARRAY_SIZE(args), val,
+				  ARRAY_SIZE(val), DEFAULT_TIMEOUT);
+
+	*frequency = compose_u16(val[3], val[4]);
+	return err;
+}
+
+
+static int si4713_set_power_state(struct si4763_device *sdev, u8 value)
+{
+	int rval;
+
+	mutex_lock(&sdev->mutex);
+
+	if (value)
+		rval = si4713_powerup(sdev);
+	else
+		rval = si4713_powerdown(sdev);
+
+	mutex_unlock(&sdev->mutex);
+	return rval;
+}
+
+
+/*
+ * si4713_initialize - Sets the device up with default configuration.
+ * @sdev: si4713_device structure for the device we are communicating
+ */
+static int si4713_initialize(struct si4763_device *sdev)
+{
+	int rval;
+
+	rval = si4713_set_power_state(sdev, POWER_OFF);
+	if (rval < 0)
+		goto exit;
+
+	rval = si4713_set_power_state(sdev, POWER_ON);
+	if (rval < 0)
+		goto exit;
+
+	rval = si4713_checkrev(sdev);
+	if (rval < 0)
+		goto exit;
+	rval = si4713_set_power_state(sdev, POWER_OFF);
+	if (rval < 0)
+		goto exit;
+
+exit:
+	return rval;
+}
+
+static int si4763_setup(struct si4763_device *sdev)
+{
+	int rval;
+	u32 temp;
+	rval = si4713_write_property(sdev, 0x0202, 0xBB80);
+	if (rval < 0)
+		goto exit;
+
+	rval = si4713_write_property(sdev, 0x0203, 0x0400);
+	if (rval < 0)
+		goto exit;
+	rval = si4713_tx_tune_freq(sdev, FREQ_RANGE_LOW);
+	if (rval < 0)
+		goto exit;
+
+	rval = si4713_enable_digitalout(sdev);
+	if (rval < 0)
+		goto exit;
+
+	rval = si4713_get_digitalout(sdev, &temp);
+	if (rval < 0)
+		goto exit;
+
+exit:
+	return rval;
+}
+
+/*
+ * Video4Linux Subdev Interface
+ */
+
+/* si4713_ioctl - deal with private ioctls (only rnl for now) */
+long si4713_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+	struct si4763_device *sdev = to_si4763_device(sd);
+	struct si4713_rnl *rnl = arg;
+	int frequency = 0;
+	int rval = 0;
+
+	if (!arg)
+		return -EINVAL;
+
+	mutex_lock(&sdev->mutex);
+	switch (cmd) {
+	case SI4713_IOC_MEASURE_RNL:
+
+		if (sdev->power_state) {
+			/* Set desired measurement frequency */
+			rval = si4713_tx_tune_measure(sdev, frequency, 0);
+			if (rval < 0)
+				goto unlock;
+			/* get results from tune status */
+		}
+		rnl->rnl = sdev->tune_rnl;
+		break;
+
+	default:
+		/* nothing */
+		rval = -ENOIOCTLCMD;
+	}
+
+unlock:
+	mutex_unlock(&sdev->mutex);
+	return rval;
+}
+
+
+/* si4763_g_frequency - get tuner or modulator radio frequency */
+static int si4763_g_frequency(struct file *file, void *priv,
+		struct v4l2_frequency *f)
+{
+
+	struct si4763_device *sdev = video_drvdata(file);
+	int rval = 0;
+
+	f->type = V4L2_TUNER_RADIO;
+
+	mutex_lock(&sdev->mutex);
+
+	if (sdev->power_state) {
+		u16 freq;
+
+		rval = si4763_fm_rsq_status(sdev, &freq);
+		if (rval < 0)
+			goto unlock;
+
+		sdev->frequency = freq;
+	}
+
+	f->frequency = sdev->frequency;
+
+unlock:
+	mutex_unlock(&sdev->mutex);
+	return rval;
+}
+
+/* si4713_s_frequency - set tuner or modulator radio frequency */
+static int si4763_s_frequency(struct file *file, void *priv,
+	struct v4l2_frequency *f)
+
+{
+	struct si4763_device *sdev = video_drvdata(file);
+	int rval = 0;
+	u16 frequency = f->frequency;
+
+	/* Check frequency range */
+	if (frequency < FREQ_RANGE_LOW || frequency > FREQ_RANGE_HIGH)
+		return -EDOM;
+
+	mutex_lock(&sdev->mutex);
+
+	if (sdev->power_state) {
+		rval = si4713_tx_tune_freq(sdev, frequency);
+		if (rval < 0)
+			goto unlock;
+		frequency = rval;
+		rval = 0;
+	}
+	sdev->frequency = frequency;
+	f->frequency = frequency;
+
+unlock:
+	mutex_unlock(&sdev->mutex);
+	return rval;
+}
+
+
+/**************************************************************************
+ * File Operations Interface
+ **************************************************************************/
+
+/*
+ * si4763_fops_open - file open
+ */
+int si4763_fops_open(struct file *file)
+{
+	struct si4763_device *radio = video_drvdata(file);
+	int retval = 0;
+
+	if (radio->users != 0)
+		return -ENODEV;
+	/* start radio */
+	si4713_set_power_state(radio, POWER_ON);
+	si4763_setup(radio);
+	radio->users = 1;
+
+	return retval;
+}
+
+
+/*
+ * si470x_fops_release - file release
+ */
+int si4763_fops_release(struct file *file)
+{
+	struct si4763_device *radio = video_drvdata(file);
+	int retval = 0;
+
+	/* safety check */
+	if (!radio)
+		return -ENODEV;
+
+
+	/* stop radio */
+	si4713_set_power_state(radio, POWER_OFF);
+	radio->users = 0;
+	return retval;
+}
+
+
+/*
+ * si4763_fops - file operations interface
+ * video_ioctl2 is part of the v4l2 implementations. Change this pointer to the
+ * ioctl function you want to implement, in case you don't want to be part of
+ * v4l2.
+ */
+static const struct v4l2_file_operations si4763_fops = {
+	.owner                  = THIS_MODULE,
+	.ioctl                  = video_ioctl2,
+	.open                   = si4763_fops_open,
+	.release                = si4763_fops_release,
+};
+
+
+/*
+ * si4763_ioctl_ops - video device ioctl operations
+ */
+static const struct v4l2_ioctl_ops si4763_ioctl_ops = {
+	.vidioc_g_frequency     = si4763_g_frequency,
+	.vidioc_s_frequency     = si4763_s_frequency,
+};
+
+
+/*
+ * si4763_viddev_template - video device interface
+ */
+struct video_device si4763_viddev_template = {
+	.fops                   = &si4763_fops,
+	.name                   = "si4763_i2c",
+	.release                = video_device_release,
+	.ioctl_ops              = &si4763_ioctl_ops,
+};
+
+
+/*
+ * I2C driver interface
+ */
+/* si4713_probe - probe for the device */
+static int si4713_probe(struct i2c_client *client,
+					const struct i2c_device_id *id)
+{
+	struct si4763_device *sdev;
+	int rval;
+
+	sdev = kzalloc(sizeof *sdev, GFP_KERNEL);
+	if (!sdev) {
+		dev_err(&client->dev, "Failed to alloc video device.\n");
+		rval = -ENOMEM;
+		goto exit;
+	}
+	sdev->client = client;
+	sdev->users = 0;
+	/* video device allocation and initialization */
+	sdev->videodev = video_device_alloc();
+	if (!sdev->videodev) {
+		rval = -ENOMEM;
+		goto free_video;
+	}
+
+
+	mutex_init(&sdev->mutex);
+	memcpy(sdev->videodev, &si4763_viddev_template,
+			sizeof(si4763_viddev_template));
+	video_set_drvdata(sdev->videodev, sdev);
+/*
+	if (client->irq) {
+		rval = request_irq(client->irq,
+			si4713_handler, IRQF_TRIGGER_FALLING | IRQF_DISABLED,
+			client->name, sdev);
+		if (rval < 0) {
+			v4l2_err(&sdev->sd, "Could not request IRQ\n");
+			goto put_reg;
+		}
+		v4l2_dbg(1, debug, &sdev->sd, "IRQ requested.\n");
+	} else {
+		v4l2_warn(&sdev->sd, "IRQ not configured. Using timeouts.\n");
+	}
+*/
+
+	rval = si4713_initialize(sdev);
+	if (rval < 0) {
+		v4l2_err(&sdev->sd, "Failed to probe device information.\n");
+		goto free_sdev;
+	}
+
+	/* register video device */
+	rval = video_register_device(sdev->videodev, VFL_TYPE_RADIO,
+			radio_nr);
+	if (rval) {
+		dev_warn(&client->dev, "Could not register video device\n");
+		goto free_video;
+	}
+	i2c_set_clientdata(client, sdev);
+	return 0;
+
+free_video:
+	video_device_release(sdev->videodev);
+
+free_sdev:
+	kfree(sdev);
+exit:
+	return rval;
+}
+
+/* si4713_remove - remove the device */
+static int si4713_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct si4763_device *sdev = to_si4763_device(sd);
+
+	if (sdev->power_state)
+		si4713_set_power_state(sdev, POWER_DOWN);
+
+	if (client->irq > 0)
+		free_irq(client->irq, sdev);
+
+	v4l2_device_unregister_subdev(sd);
+	kfree(sdev);
+
+	return 0;
+}
+
+/* si4713_i2c_driver - i2c driver interface */
+static const struct i2c_device_id si4713_id[] = {
+	{ "si4763_i2c" , 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, si4713_id);
+
+static struct i2c_driver si4713_i2c_driver = {
+	.driver		= {
+		.name	= "si4763_i2c",
+	},
+	.probe		= si4713_probe,
+	.remove         = si4713_remove,
+	.id_table       = si4713_id,
+};
+
+/* Module Interface */
+static int __init si4713_module_init(void)
+{
+	return i2c_add_driver(&si4713_i2c_driver);
+}
+
+static void __exit si4713_module_exit(void)
+{
+	i2c_del_driver(&si4713_i2c_driver);
+}
+
+module_init(si4713_module_init);
+module_exit(si4713_module_exit);
+
+/* Module information */
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("I2C si4763");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/radio/si4763-i2c.h b/drivers/media/radio/si4763-i2c.h
new file mode 100644
index 000000000000..d97eb35863da
--- /dev/null
+++ b/drivers/media/radio/si4763-i2c.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef SI4763_I2C_H
+#define SI4763_I2C_H
+
+#include <media/v4l2-subdev.h>
+#include <media/si4763.h>
+
+#define SI4760_PRODUCT_NUMBER		0x05
+
+/* Command Timeouts */
+#define DEFAULT_TIMEOUT			500
+#define TIMEOUT_SET_PROPERTY		20
+#define TIMEOUT_TX_TUNE_POWER		30000
+#define TIMEOUT_TX_TUNE			110000
+#define TIMEOUT_POWER_UP		200000
+
+/*
+ * Command and its arguments definitions
+ */
+#define SI4713_PWUP_CTSIEN		(1<<7)
+#define SI4713_PWUP_GPO2OEN		(1<<6)
+#define SI4713_PWUP_PATCH		(1<<5)
+#define SI4713_PWUP_XOSCEN		(1<<4)
+#define SI4713_PWUP_FUNC_TX		0x02
+#define SI4713_PWUP_FUNC_PATCH		0x0F
+#define SI4713_PWUP_OPMOD_ANALOG	0x50
+#define SI4713_PWUP_OPMOD_DIGITAL	0x0F
+#define SI4760_PWUP_NARGS		5
+#define SI4760_PWUP_NRESP		1
+#define SI4760_PWDOWN_NARGS             1
+
+#define SI4760_CMD_POWER_UP		0x01
+
+#define SI4760_PWUP_ARG1               0xF7
+#define SI4760_PWUP_ARG2               0x28
+#define SI4760_PWUP_ARG3               0x07
+#define SI4760_PWUP_ARG4               0x11
+#define SI4760_PWUP_ARG5               0x11
+
+#define SI4713_CMD_EN_DIGITALOUT	0x18
+#define SI4713_EN_DIGITALOUT_NARGS	4
+
+
+#define SI4760_GETREV_NRESP		9
+#define SI4760_CMD_GET_REV		0x02
+
+#define SI4760_PWDN_NRESP		1
+#define SI4760_CMD_POWER_DOWN		0x11
+
+#define SI4763_CMD_FM_RSQ_STATUS	0x32
+#define SI4763_FM_RSQ_STATUS_NARGS	1
+#define SI4763_FM_RSQ_STATUS_NRESP      5
+
+#define SI4713_SET_PROP_NARGS		5
+#define SI4713_SET_PROP_NRESP		1
+#define SI4713_CMD_SET_PROPERTY		0x13
+
+#define SI4713_GET_PROP_NARGS		3
+#define SI4713_GET_PROP_NRESP		4
+#define SI4713_CMD_GET_PROPERTY		0x13
+
+#define SI4713_GET_STATUS_NRESP		1
+#define SI4713_CMD_GET_INT_STATUS	0x14
+
+#define SI4713_CMD_PATCH_ARGS		0x15
+#define SI4713_CMD_PATCH_DATA		0x16
+
+#define SI4713_MAX_FREQ			10800
+#define SI4713_MIN_FREQ			7600
+#define SI4713_TXFREQ_NARGS		5
+#define SI4713_TXFREQ_NRESP		1
+#define SI4713_CMD_TX_TUNE_FREQ		0x30
+
+#define SI4713_MAX_POWER		120
+#define SI4713_MIN_POWER		88
+#define SI4713_MAX_ANTCAP		191
+#define SI4713_MIN_ANTCAP		0
+#define SI4713_TXPWR_NARGS		4
+#define SI4713_TXPWR_NRESP		1
+#define SI4713_CMD_TX_TUNE_POWER	0x31
+
+#define SI4713_TXMEA_NARGS		4
+#define SI4713_TXMEA_NRESP		1
+#define SI4713_CMD_TX_TUNE_MEASURE	0x32
+
+#define SI4713_INTACK_MASK		0x01
+#define SI4713_TXSTATUS_NARGS		1
+#define SI4713_TXSTATUS_NRESP		8
+#define SI4713_CMD_TX_TUNE_STATUS	0x33
+
+#define SI4713_OVERMOD_BIT		(1 << 2)
+#define SI4713_IALH_BIT			(1 << 1)
+#define SI4713_IALL_BIT			(1 << 0)
+#define SI4713_ASQSTATUS_NARGS		1
+#define SI4713_ASQSTATUS_NRESP		5
+#define SI4713_CMD_TX_ASQ_STATUS	0x34
+
+#define SI4713_RDSBUFF_MODE_MASK	0x87
+#define SI4713_RDSBUFF_NARGS		7
+#define SI4713_RDSBUFF_NRESP		6
+#define SI4713_CMD_TX_RDS_BUFF		0x35
+
+#define SI4713_RDSPS_PSID_MASK		0x1F
+#define SI4713_RDSPS_NARGS		5
+#define SI4713_RDSPS_NRESP		1
+#define SI4713_CMD_TX_RDS_PS		0x36
+
+#define SI4713_CMD_GPO_CTL		0x80
+#define SI4713_CMD_GPO_SET		0x81
+
+/*
+ * Bits from status response
+ */
+#define SI4713_CTS			(1<<7)
+#define SI4713_ERR			(1<<6)
+#define SI4713_RDS_INT			(1<<2)
+#define SI4713_ASQ_INT			(1<<1)
+#define SI4713_STC_INT			(1<<0)
+
+/*
+ * Property definitions
+ */
+#define SI4713_GPO_IEN			0x0001
+#define SI4713_DIG_INPUT_FORMAT		0x0101
+#define SI4713_DIG_INPUT_SAMPLE_RATE	0x0103
+#define SI4713_REFCLK_FREQ		0x0201
+#define SI4713_REFCLK_PRESCALE		0x0202
+#define SI4713_TX_COMPONENT_ENABLE	0x2100
+#define SI4713_TX_AUDIO_DEVIATION	0x2101
+#define SI4713_TX_PILOT_DEVIATION	0x2102
+#define SI4713_TX_RDS_DEVIATION		0x2103
+#define SI4713_TX_LINE_INPUT_LEVEL	0x2104
+#define SI4713_TX_LINE_INPUT_MUTE	0x2105
+#define SI4713_TX_PREEMPHASIS		0x2106
+#define SI4713_TX_PILOT_FREQUENCY	0x2107
+#define SI4713_TX_ACOMP_ENABLE		0x2200
+#define SI4713_TX_ACOMP_THRESHOLD	0x2201
+#define SI4713_TX_ACOMP_ATTACK_TIME	0x2202
+#define SI4713_TX_ACOMP_RELEASE_TIME	0x2203
+#define SI4713_TX_ACOMP_GAIN		0x2204
+#define SI4713_TX_LIMITER_RELEASE_TIME	0x2205
+#define SI4713_TX_ASQ_INTERRUPT_SOURCE	0x2300
+#define SI4713_TX_ASQ_LEVEL_LOW		0x2301
+#define SI4713_TX_ASQ_DURATION_LOW	0x2302
+#define SI4713_TX_ASQ_LEVEL_HIGH	0x2303
+#define SI4713_TX_ASQ_DURATION_HIGH	0x2304
+#define SI4713_TX_RDS_INTERRUPT_SOURCE	0x2C00
+#define SI4713_TX_RDS_PI		0x2C01
+#define SI4713_TX_RDS_PS_MIX		0x2C02
+#define SI4713_TX_RDS_PS_MISC		0x2C03
+#define SI4713_TX_RDS_PS_REPEAT_COUNT	0x2C04
+#define SI4713_TX_RDS_PS_MESSAGE_COUNT	0x2C05
+#define SI4713_TX_RDS_PS_AF		0x2C06
+#define SI4713_TX_RDS_FIFO_SIZE		0x2C07
+
+#define PREEMPHASIS_USA			75
+#define PREEMPHASIS_EU			50
+#define PREEMPHASIS_DISABLED		0
+#define FMPE_USA			0x00
+#define FMPE_EU				0x01
+#define FMPE_DISABLED			0x02
+
+#define POWER_UP			0x01
+#define POWER_DOWN			0x00
+
+struct rds_info {
+	u32 pi;
+#define MAX_RDS_PTY			31
+	u32 pty;
+#define MAX_RDS_DEVIATION		90000
+	u32 deviation;
+/*
+ * PSNAME is known to be defined as 8 character sized (RDS Spec).
+ * However, there is receivers which scroll PSNAME 8xN sized.
+ */
+#define MAX_RDS_PS_NAME			96
+	u8 ps_name[MAX_RDS_PS_NAME + 1];
+/*
+ * MAX_RDS_RADIO_TEXT is known to be defined as 32 (2A group) or 64 (2B group)
+ * character sized (RDS Spec).
+ * However, there is receivers which scroll them as well.
+ */
+#define MAX_RDS_RADIO_TEXT		384
+	u8 radio_text[MAX_RDS_RADIO_TEXT + 1];
+	u32 enabled;
+};
+
+struct limiter_info {
+#define MAX_LIMITER_RELEASE_TIME	102390
+	u32 release_time;
+#define MAX_LIMITER_DEVIATION		90000
+	u32 deviation;
+	u32 enabled;
+};
+
+struct pilot_info {
+#define MAX_PILOT_DEVIATION		90000
+	u32 deviation;
+#define MAX_PILOT_FREQUENCY		19000
+	u32 frequency;
+	u32 enabled;
+};
+
+struct acomp_info {
+#define MAX_ACOMP_RELEASE_TIME		1000000
+	u32 release_time;
+#define MAX_ACOMP_ATTACK_TIME		5000
+	u32 attack_time;
+#define MAX_ACOMP_THRESHOLD		0
+#define MIN_ACOMP_THRESHOLD		(-40)
+	s32 threshold;
+#define MAX_ACOMP_GAIN			20
+	u32 gain;
+	u32 enabled;
+};
+
+#define SI4763_NUM_SUPPLIES		2
+
+/*
+ * si4763_device - private data
+ */
+struct si4763_device {
+	/* v4l2_subdev and i2c reference (v4l2_subdev priv data) */
+	struct v4l2_subdev sd;
+	/* private data structures */
+	struct mutex mutex;
+	struct completion work;
+	struct rds_info rds_info;
+	struct limiter_info limiter_info;
+	struct pilot_info pilot_info;
+	struct acomp_info acomp_info;
+	struct regulator_bulk_data supplies[SI4763_NUM_SUPPLIES];
+	int gpio_reset;
+	u32 frequency;
+	u32 preemphasis;
+	u32 mute;
+	u32 power_level;
+	u32 power_state;
+	u32 antenna_capacitor;
+	u32 stereo;
+	u32 tune_rnl;
+	u8 users;
+	struct i2c_client *client;
+	struct video_device *videodev;
+};
+#endif /* ifndef SI4763_I2C_H */
diff --git a/drivers/media/video/mxc/output/mxc_vout.c b/drivers/media/video/mxc/output/mxc_vout.c
index 43b53678d5ca..7542ca5f2062 100644
--- a/drivers/media/video/mxc/output/mxc_vout.c
+++ b/drivers/media/video/mxc/output/mxc_vout.c
@@ -30,6 +30,22 @@
 
 #define MAX_FB_NUM	6
 #define FB_BUFS		3
+#define VALID_HEIGHT_1080P	(1080)
+#define FRAME_HEIGHT_1080P	(1088)
+#define FRAME_WIDTH_1080P	(1920)
+#define MAX_INTERLACED_WIDTH	(1024)
+#define CHECK_TILED_1080P_DISPLAY(vout)	\
+	(((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) &&	\
+	       ((vout)->task.input.width == FRAME_WIDTH_1080P) &&	\
+	       ((vout)->task.output.crop.w == FRAME_WIDTH_1080P) &&	\
+	       ((vout)->task.input.height == FRAME_HEIGHT_1080P) &&	\
+	       ((vout)->task.output.crop.h == VALID_HEIGHT_1080P))
+#define CHECK_TILED_1080P_STREAM(vout)	\
+	(((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) &&	\
+	       ((vout)->task.input.width == FRAME_WIDTH_1080P) &&	\
+	       ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) &&	\
+	       ((vout)->task.input.height == FRAME_HEIGHT_1080P) &&	\
+	       ((vout)->task.input.crop.h == FRAME_HEIGHT_1080P))
 
 struct mxc_vout_fb {
 	char *name;
@@ -62,7 +78,14 @@ struct mxc_vout_output {
 
 	bool fmt_init;
 	bool bypass_pp;
+	bool is_vdoaipu_task;
 	struct ipu_task	task;
+	struct ipu_task	vdoa_task;
+	struct vdoa_mem {
+		void *vaddr;
+		dma_addr_t paddr;
+		size_t size;
+	} vdoa_dma;
 
 	bool timer_stop;
 	struct timer_list timer;
@@ -97,7 +120,7 @@ static int video_nr = 16;
 /* Module parameters */
 module_param(video_nr, int, S_IRUGO);
 MODULE_PARM_DESC(video_nr, "video device numbers");
-module_param(debug, bool, S_IRUGO);
+module_param(debug, int, 0600);
 MODULE_PARM_DESC(debug, "Debug level (0-1)");
 
 const static struct v4l2_fmtdesc mxc_formats[] = {
@@ -145,6 +168,14 @@ const static struct v4l2_fmtdesc mxc_formats[] = {
 		.description = "YUV420",
 		.pixelformat = V4L2_PIX_FMT_YUV420,
 	},
+	{
+		.description = "TILED NV12P",
+		.pixelformat = IPU_PIX_FMT_TILED_NV12,
+	},
+	{
+		.description = "TILED NV12F",
+		.pixelformat = IPU_PIX_FMT_TILED_NV12F,
+	},
 };
 
 #define NUM_MXC_VOUT_FORMATS (ARRAY_SIZE(mxc_formats))
@@ -158,6 +189,24 @@ static struct mxc_vout_fb g_fb_setting[MAX_FB_NUM];
 static int config_disp_output(struct mxc_vout_output *vout);
 static void release_disp_output(struct mxc_vout_output *vout);
 
+static unsigned int get_frame_size(struct mxc_vout_output *vout)
+{
+	unsigned int size;
+
+	if (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)
+		size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
+					vout->task.input.height);
+	else if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
+		size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
+					vout->task.input.height/2);
+		size *= 2;
+	} else
+		size = vout->task.input.width * vout->task.input.height *
+				fmt_to_bpp(vout->task.input.format)/8;
+
+	return size;
+}
+
 static ipu_channel_t get_ipu_channel(struct fb_info *fbi)
 {
 	ipu_channel_t ipu_ch = CHAN_NONE;
@@ -315,6 +364,9 @@ static bool deinterlace_3_field(struct mxc_vout_output *vout)
 
 static bool is_pp_bypass(struct mxc_vout_output *vout)
 {
+	if ((IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) ||
+		(IPU_PIX_FMT_TILED_NV12F == vout->task.input.format))
+		return false;
 	if ((vout->task.input.width == vout->task.output.width) &&
 		(vout->task.input.height == vout->task.output.height) &&
 		(vout->task.input.crop.w == vout->task.output.crop.w) &&
@@ -374,6 +426,8 @@ static int show_buf(struct mxc_vout_output *vout, int idx,
 	struct fb_info *fbi = vout->fbi;
 	struct fb_var_screeninfo var;
 	int ret;
+	u32 is_1080p;
+	u32 yres = 0;
 
 	memcpy(&var, &fbi->var, sizeof(var));
 
@@ -390,9 +444,17 @@ static int show_buf(struct mxc_vout_output *vout, int idx,
 		ret = fb_pan_display(fbi, &var);
 		console_unlock();
 	} else {
-		var.yoffset = idx * fbi->var.yres;
 		console_lock();
+		is_1080p = CHECK_TILED_1080P_DISPLAY(vout);
+		if (is_1080p) {
+			yres = fbi->var.yres;
+			fbi->var.yres = FRAME_HEIGHT_1080P;
+		}
+
+		var.yoffset = idx * fbi->var.yres;
 		ret = fb_pan_display(fbi, &var);
+		if (is_1080p)
+			fbi->var.yres = yres;
 		console_unlock();
 	}
 
@@ -408,6 +470,8 @@ static void disp_work_func(struct work_struct *work)
 	unsigned long flags = 0;
 	struct ipu_pos ipos;
 	int ret = 0;
+	u32 is_1080p;
+	u32 ocrop_h = 0;
 
 	v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work begin one frame\n");
 
@@ -458,11 +522,31 @@ static void disp_work_func(struct work_struct *work)
 		}
 		vout->task.output.paddr =
 			vout->disp_bufs[vout->frame_count % FB_BUFS];
+
+		is_1080p = CHECK_TILED_1080P_DISPLAY(vout);
+		if (is_1080p) {
+			vout->task.input.crop.h = FRAME_HEIGHT_1080P;
+			vout->task.output.height = FRAME_HEIGHT_1080P;
+			ocrop_h = vout->task.output.crop.h;
+			vout->task.output.crop.h = FRAME_HEIGHT_1080P;
+		}
+		if (vout->is_vdoaipu_task) {
+			vout->vdoa_task.input.paddr = vout->task.input.paddr;
+			vout->vdoa_task.output.paddr = vout->vdoa_dma.paddr;
+			ret = ipu_queue_task(&vout->vdoa_task);
+			if (ret < 0) {
+				mutex_unlock(&vout->task_lock);
+				goto err;
+			}
+			vout->task.input.paddr = vout->vdoa_task.output.paddr;
+		}
 		ret = ipu_queue_task(&vout->task);
 		if (ret < 0) {
 			mutex_unlock(&vout->task_lock);
 			goto err;
 		}
+		if (is_1080p)
+			vout->task.output.crop.h = ocrop_h;
 	}
 
 	mutex_unlock(&vout->task_lock);
@@ -569,6 +653,7 @@ static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
 			  unsigned int *size)
 {
 	struct mxc_vout_output *vout = q->priv_data;
+	unsigned int frame_size;
 
 	if (!vout)
 		return -EINVAL;
@@ -576,8 +661,8 @@ static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
 	if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type)
 		return -EINVAL;
 
-	*size = PAGE_ALIGN(vout->task.input.width * vout->task.input.height *
-			fmt_to_bpp(vout->task.input.format)/8);
+	frame_size = get_frame_size(vout);
+	*size = PAGE_ALIGN(frame_size);
 
 	return 0;
 }
@@ -758,8 +843,7 @@ static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
 	f->fmt.pix.width = vout->task.input.width;
 	f->fmt.pix.height = vout->task.input.height;
 	f->fmt.pix.pixelformat = vout->task.input.format;
-	f->fmt.pix.sizeimage = vout->task.input.width * vout->task.input.height *
-			fmt_to_bpp(vout->task.input.format)/8;
+	f->fmt.pix.sizeimage = get_frame_size(vout);
 
 	if (f->fmt.pix.priv) {
 		rect = (struct v4l2_rect *)f->fmt.pix.priv;
@@ -768,6 +852,10 @@ static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
 		rect->width = vout->task.input.crop.w;
 		rect->height = vout->task.input.crop.h;
 	}
+	v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+			"frame_size:0x%x, pix_fmt:0x%x\n",
+			f->fmt.pix.sizeimage,
+			vout->task.input.format);
 
 	return 0;
 }
@@ -813,33 +901,128 @@ again:
 	return ret;
 }
 
+static inline int vdoaipu_try_task(struct mxc_vout_output *vout)
+{
+	int ret;
+	u32 icrop_h = 0, icrop_w = 0;
+	int is_1080p_stream;
+	size_t size;
+	struct ipu_task *ipu_task = &vout->task;
+	struct ipu_task *vdoa_task = &vout->vdoa_task;
+
+	is_1080p_stream = CHECK_TILED_1080P_STREAM(vout);
+	if (is_1080p_stream)
+		ipu_task->input.crop.h = VALID_HEIGHT_1080P;
+
+	if (ipu_task->input.crop.h % IPU_PIX_FMT_TILED_NV12_MBALIGN) {
+		icrop_h = ipu_task->input.crop.h;
+		ipu_task->input.crop.h = ALIGN(ipu_task->input.crop.h,
+						IPU_PIX_FMT_TILED_NV12_MBALIGN);
+	}
+	if (ipu_task->input.crop.w % IPU_PIX_FMT_TILED_NV12_MBALIGN) {
+		icrop_w = ipu_task->input.crop.w;
+		ipu_task->input.crop.w = ALIGN(ipu_task->input.crop.w,
+						IPU_PIX_FMT_TILED_NV12_MBALIGN);
+	}
+
+	memset(vdoa_task, 0, sizeof(*vdoa_task));
+	memcpy(&vdoa_task->input, &ipu_task->input, sizeof(ipu_task->input));
+	vdoa_task->output.format = IPU_PIX_FMT_NV12;
+	vdoa_task->output.width = ipu_task->input.crop.w;
+	vdoa_task->output.height = ipu_task->input.crop.h;
+	vdoa_task->output.crop.w = ipu_task->input.crop.w;
+	vdoa_task->output.crop.h = ipu_task->input.crop.h;
+
+	size = PAGE_ALIGN(ipu_task->input.crop.w *
+					ipu_task->input.crop.h *
+					fmt_to_bpp(vdoa_task->output.format)/8);
+	if (size > vout->vdoa_dma.size) {
+		if (vout->vdoa_dma.vaddr) {
+			dma_free_coherent(vout->vbq.dev, vout->vdoa_dma.size,
+				vout->vdoa_dma.vaddr, vout->vdoa_dma.paddr);
+			v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+					"free vdoa_dma.size:0x%x, paddr:0x%x\n",
+					vout->vdoa_dma.size,
+					vout->vdoa_dma.paddr);
+			memset(&vout->vdoa_dma, 0, sizeof(vout->vdoa_dma));
+		}
+		vout->vdoa_dma.size = size;
+		vout->vdoa_dma.vaddr = dma_alloc_coherent(vout->vbq.dev,
+							vout->vdoa_dma.size,
+							&vout->vdoa_dma.paddr,
+							GFP_DMA | GFP_KERNEL);
+		if (!vout->vdoa_dma.vaddr)
+			return -ENOMEM;
+		v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+				"alloc vdoa_dma.size:0x%x, paddr:0x%x\n",
+				vout->vdoa_dma.size,
+				vout->vdoa_dma.paddr);
+	}
+	ret = ipu_check_task(vdoa_task);
+	if (ret != IPU_CHECK_OK)
+		return -EINVAL;
+
+	ipu_task->input.format = vdoa_task->output.format;
+	if (icrop_h) {
+		ipu_task->input.height = vdoa_task->output.height;
+		ipu_task->input.crop.h = icrop_h;
+	}
+	if (icrop_w) {
+		ipu_task->input.width = vdoa_task->output.width;
+		ipu_task->input.crop.w = icrop_w;
+	}
+	ret = ipu_try_task(vout);
+
+	return ret;
+}
+
 static int mxc_vout_try_task(struct mxc_vout_output *vout)
 {
 	int ret = 0;
+	struct ipu_output *output = &vout->task.output;
+	struct ipu_input *input = &vout->task.input;
 
-	vout->task.input.crop.w -= vout->task.input.crop.w%8;
-	vout->task.input.crop.h -= vout->task.input.crop.h%8;
-
+	input->crop.w -= input->crop.w%8;
+	input->crop.h -= input->crop.h%8;
 	/* assume task.output already set by S_CROP */
 	if (is_pp_bypass(vout)) {
 		v4l2_info(vout->vfd->v4l2_dev, "Bypass IC.\n");
 		vout->bypass_pp = true;
-		vout->task.output.format = vout->task.input.format;
+		output->format = input->format;
 	} else {
 		/* if need CSC, choose IPU-DP or IPU_IC do it */
 		vout->bypass_pp = false;
 		if (vout->disp_support_csc) {
-			if (colorspaceofpixel(vout->task.input.format) == YUV_CS)
-				vout->task.output.format = IPU_PIX_FMT_UYVY;
+			if (colorspaceofpixel(input->format) == YUV_CS)
+				output->format = IPU_PIX_FMT_UYVY;
 			else
-				vout->task.output.format = IPU_PIX_FMT_RGB565;
+				output->format = IPU_PIX_FMT_RGB565;
 		} else {
 			if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
-				vout->task.output.format = IPU_PIX_FMT_UYVY;
+				output->format = IPU_PIX_FMT_UYVY;
+			else
+				output->format = IPU_PIX_FMT_RGB565;
+		}
+
+		vout->is_vdoaipu_task = 0;
+		if ((IPU_PIX_FMT_TILED_NV12 == input->format) ||
+			(IPU_PIX_FMT_TILED_NV12F == input->format)) {
+			/* check resize/rotate/flip, or csc task */
+			if ((IPU_ROTATE_NONE != output->rotate) ||
+				(input->crop.w != output->crop.w) ||
+				(input->crop.h != output->crop.h) ||
+				(!vout->disp_support_csc &&
+				(colorspaceofpixel(vout->disp_fmt) == RGB_CS)))
+				vout->is_vdoaipu_task = 1;
 			else
-				vout->task.output.format = IPU_PIX_FMT_RGB565;
+				/* IC bypass */
+				output->format = IPU_PIX_FMT_NV12;
 		}
-		ret = ipu_try_task(vout);
+
+		if (vout->is_vdoaipu_task)
+			ret = vdoaipu_try_task(vout);
+		else
+			ret = ipu_try_task(vout);
 	}
 
 	return ret;
@@ -849,11 +1032,23 @@ static int mxc_vout_try_format(struct mxc_vout_output *vout, struct v4l2_format
 {
 	int ret = 0;
 	struct v4l2_rect *rect = NULL;
+	u32 o_height = 0;
+	u32 ocrop_h = 0;
+	u32 is_1080p;
 
 	vout->task.input.width = f->fmt.pix.width;
 	vout->task.input.height = f->fmt.pix.height;
 	vout->task.input.format = f->fmt.pix.pixelformat;
 
+	if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
+		if (vout->task.input.width > MAX_INTERLACED_WIDTH)
+			return -EINVAL;
+		v4l2_info(vout->vfd->v4l2_dev,
+				"tiled fmt enable deinterlace.\n");
+		vout->task.input.deinterlace.enable = true;
+		vout->task.input.deinterlace.field_fmt =
+				IPU_DEINTERLACE_FIELD_TOP;
+	}
 	switch (f->fmt.pix.field) {
 	/* Images are in progressive format, not interlaced */
 	case V4L2_FIELD_NONE:
@@ -893,6 +1088,15 @@ static int mxc_vout_try_format(struct mxc_vout_output *vout, struct v4l2_format
 		vout->task.input.crop.h = f->fmt.pix.height;
 	}
 
+	is_1080p = CHECK_TILED_1080P_DISPLAY(vout);
+	if (is_1080p) {
+		vout->task.input.crop.h = FRAME_HEIGHT_1080P;
+		o_height = vout->task.output.height;
+		ocrop_h = vout->task.output.crop.h;
+		vout->task.output.height = FRAME_HEIGHT_1080P;
+		vout->task.output.crop.h = FRAME_HEIGHT_1080P;
+	}
+
 	ret = mxc_vout_try_task(vout);
 	if (!ret) {
 		if (rect) {
@@ -904,6 +1108,11 @@ static int mxc_vout_try_format(struct mxc_vout_output *vout, struct v4l2_format
 		}
 	}
 
+	if (is_1080p) {
+		vout->task.output.height = o_height;
+		vout->task.output.crop.h = ocrop_h;
+	}
+
 	return ret;
 }
 
@@ -1311,6 +1520,7 @@ static int config_disp_output(struct mxc_vout_output *vout)
 	struct fb_info *fbi = vout->fbi;
 	struct fb_var_screeninfo var;
 	int i, display_buf_size, fb_num, ret;
+	u32 is_1080p;
 
 	memcpy(&var, &fbi->var, sizeof(var));
 
@@ -1332,7 +1542,11 @@ static int config_disp_output(struct mxc_vout_output *vout)
 	} else {
 		fb_num = FB_BUFS;
 		var.xres_virtual = var.xres;
-		var.yres_virtual = fb_num * var.yres;
+		is_1080p = CHECK_TILED_1080P_DISPLAY(vout);
+		if (is_1080p)
+			var.yres_virtual = fb_num * FRAME_HEIGHT_1080P;
+		else
+			var.yres_virtual = fb_num * var.yres;
 		var.vmode &= ~FB_VMODE_YWRAP;
 	}
 	var.bits_per_pixel = fmt_to_bpp(vout->task.output.format);
@@ -1357,7 +1571,11 @@ static int config_disp_output(struct mxc_vout_output *vout)
 	if (ret < 0)
 		return ret;
 
-	display_buf_size = fbi->fix.line_length * fbi->var.yres;
+	is_1080p = CHECK_TILED_1080P_DISPLAY(vout);
+	if (is_1080p)
+		display_buf_size = fbi->fix.line_length * FRAME_HEIGHT_1080P;
+	else
+		display_buf_size = fbi->fix.line_length * fbi->var.yres;
 	for (i = 0; i < fb_num; i++)
 		vout->disp_bufs[i] = fbi->fix.smem_start + i * display_buf_size;
 
@@ -1515,6 +1733,15 @@ static void mxc_vout_free_output(struct mxc_vout_dev *dev)
 	for (i = 0; i < dev->out_num; i++) {
 		vout = dev->out[i];
 		vfd = vout->vfd;
+		if (vout->vdoa_dma.vaddr) {
+			dma_free_coherent(vout->vbq.dev, vout->vdoa_dma.size,
+				vout->vdoa_dma.vaddr, vout->vdoa_dma.paddr);
+			v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+					"free vdoa_dma.size:0x%x, paddr:0x%x\n",
+					vout->vdoa_dma.size,
+					vout->vdoa_dma.paddr);
+			memset(&vout->vdoa_dma, 0, sizeof(vout->vdoa_dma));
+		}
 		if (vfd) {
 			if (!video_is_registered(vfd))
 				video_device_release(vfd);
diff --git a/drivers/mfd/mxc-hdmi-core.c b/drivers/mfd/mxc-hdmi-core.c
index 18fd1a67ba83..92fdf710a5b1 100644
--- a/drivers/mfd/mxc-hdmi-core.c
+++ b/drivers/mfd/mxc-hdmi-core.c
@@ -64,6 +64,7 @@ int mxc_hdmi_ipu_id;
 int mxc_hdmi_disp_id;
 static struct mxc_edid_cfg hdmi_core_edid_cfg;
 static int hdmi_core_init;
+static unsigned int hdmi_dma_running;
 
 u8 hdmi_readb(unsigned int reg)
 {
@@ -243,6 +244,12 @@ static void hdmi_set_clock_regenerator_n(unsigned int value)
 {
 	u8 val;
 
+	if (!hdmi_dma_running) {
+		hdmi_writeb(value & 0xff, HDMI_AUD_N1);
+		hdmi_writeb(0, HDMI_AUD_N2);
+		hdmi_writeb(0, HDMI_AUD_N3);
+	}
+
 	hdmi_writeb(value & 0xff, HDMI_AUD_N1);
 	hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
 	hdmi_writeb((value >> 16) & 0x0f, HDMI_AUD_N3);
@@ -257,6 +264,12 @@ static void hdmi_set_clock_regenerator_cts(unsigned int cts)
 {
 	u8 val;
 
+	if (!hdmi_dma_running) {
+		hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
+		hdmi_writeb(0, HDMI_AUD_CTS2);
+		hdmi_writeb(0, HDMI_AUD_CTS3);
+	}
+
 	/* Must be set/cleared first */
 	val = hdmi_readb(HDMI_AUD_CTS3);
 	val &= ~HDMI_AUD_CTS3_CTS_MANUAL;
@@ -433,18 +446,12 @@ static void hdmi_set_clk_regenerator(void)
 		return;
 	}
 
-	clk_enable(isfr_clk);
-	clk_enable(iahb_clk);
-
 	pr_debug("%s: samplerate=%d  ratio=%d  pixelclk=%d  N=%d  cts=%d\n",
 		__func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate,
 		clk_n, clk_cts);
 
-	hdmi_set_clock_regenerator_n(clk_n);
 	hdmi_set_clock_regenerator_cts(clk_cts);
-
-	clk_disable(iahb_clk);
-	clk_disable(isfr_clk);
+	hdmi_set_clock_regenerator_n(clk_n);
 }
 
 /* Need to run this before phy is enabled the first time to prevent
@@ -464,10 +471,15 @@ void hdmi_clk_regenerator_update_pixel_clock(void)
 	hdmi_set_clk_regenerator();
 }
 
+void hdmi_set_dma_mode(unsigned int dma_running)
+{
+	hdmi_dma_running = dma_running;
+	hdmi_set_clk_regenerator();
+}
+
 void hdmi_set_sample_rate(unsigned int rate)
 {
 	sample_rate = rate;
-	hdmi_set_clk_regenerator();
 }
 
 void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg)
@@ -511,6 +523,7 @@ static int mxc_hdmi_core_probe(struct platform_device *pdev)
 #endif
 
 	hdmi_core_init = 0;
+	hdmi_dma_running = 0;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index d6f72f8c69a3..beb289133744 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -452,6 +452,8 @@ config MTD_NAND_GPMI_NAND
         depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q)
 	select MTD_PARTITIONS
 	select MTD_CMDLINE_PARTS
+	select MTC_CHAR
+	select MXS_DMA
         help
 	 Enables NAND Flash support for IMX23 or IMX28.
 	 The GPMI controller is very powerful, with the help of BCH
diff --git a/drivers/mtd/nand/gpmi-nand/bch-regs.h b/drivers/mtd/nand/gpmi-nand/bch-regs.h
index 04acf6413b16..e1478d4de587 100644
--- a/drivers/mtd/nand/gpmi-nand/bch-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/bch-regs.h
@@ -71,6 +71,7 @@
 		? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)	\
 		: ((v) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)		\
 	)
+#define BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 0x00000400
 
 #define HW_BCH_FLASH0LAYOUT1			0x00000090
 
@@ -103,4 +104,5 @@
 		? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)	\
 		: ((v) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)		\
 	)
+#define BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 0x00000400
 #endif
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 698535773ff4..1c273e4eb2b4 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -22,11 +22,15 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <mach/mxs.h>
+#include <mach/clock.h>
 
 #include "gpmi-nand.h"
 #include "gpmi-regs.h"
 #include "bch-regs.h"
 
+#define FEATURE_SIZE		4	/* p1, p2, p3, p4 */
+#define NAND_CMD_SET_FEATURE	0xef
+
 struct timing_threshod timing_default_threshold = {
 	.max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
 						BP_GPMI_TIMING0_DATA_SETUP),
@@ -37,6 +41,281 @@ struct timing_threshod timing_default_threshold = {
 	.max_dll_delay_in_ns         = 16,
 };
 
+static struct clk *mxs_dma_clk;
+
+static void setup_ddr_timing_onfi(struct gpmi_nand_data *this)
+{
+	uint32_t value;
+	struct resources  *resources = &this->resources;
+
+	/* set timing 2 register */
+	value = BF_GPMI_TIMING2_DATA_PAUSE(0x6)
+		| BF_GPMI_TIMING2_CMDADD_PAUSE(0x4)
+		| BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x2)
+		| BF_GPMI_TIMING2_PREAMBLE_DELAY(0x4)
+		| BF_GPMI_TIMING2_CE_DELAY(0x2)
+		| BF_GPMI_TIMING2_READ_LATENCY(0x2);
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2);
+
+	/* set timing 1 register */
+	__raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500),
+			resources->gpmi_regs + HW_GPMI_TIMING1);
+
+	/* Put GPMI in NAND mode, disable device reset, and make certain
+	   IRQRDY polarity is active high. */
+	value = BV_GPMI_CTRL1_GPMI_MODE__NAND
+		| BM_GPMI_CTRL1_GANGED_RDYBUSY
+		| BF_GPMI_CTRL1_WRN_DLY_SEL(0x3)
+		| (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3)
+		| (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2);
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+}
+
+/* This must be called in the context of enabling necessary clocks */
+static void common_ddr_init(struct resources *resources)
+{
+	uint32_t value;
+
+	/* [6] enable both write & read DDR DLLs */
+	value = BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON |
+		BM_GPMI_READ_DDR_DLL_CTRL_ENABLE |
+		BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) |
+		BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7);
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+
+	/* [7] reset read */
+	__raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_RESET,
+			resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+	value = value & ~BM_GPMI_READ_DDR_DLL_CTRL_RESET;
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+
+	value = BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON |
+		BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE    |
+		BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) |
+		BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7) ,
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+
+	/* [8] reset write */
+	__raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_RESET,
+			resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+
+	/* [9] wait for locks for read and write  */
+	do {
+		uint32_t read_status, write_status;
+		uint32_t r_mask, w_mask;
+
+		read_status = __raw_readl(resources->gpmi_regs
+					+ HW_GPMI_READ_DDR_DLL_STS);
+		write_status = __raw_readl(resources->gpmi_regs
+					+ HW_GPMI_WRITE_DDR_DLL_STS);
+
+		r_mask = (BM_GPMI_READ_DDR_DLL_STS_REF_LOCK |
+				BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK);
+		w_mask = (BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK |
+				BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK);
+
+		if (((read_status & r_mask) == r_mask)
+			&& ((write_status & w_mask) == w_mask))
+				break;
+	} while (1);
+
+	/* [10] force update of read/write */
+	value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+	__raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD,
+			resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+
+	value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+	__raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD,
+			resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+
+	/* [11] set gate update */
+	value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+	value |= BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE;
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
+
+	value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+	value |= BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE;
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
+}
+
+static int enable_ddr_onfi(struct gpmi_nand_data *this)
+{
+	struct resources  *resources = &this->resources;
+	struct nand_chip *nand = &this->nand;
+	struct mtd_info	 *mtd = &this->mtd;
+	int saved_chip_number = 0;
+	uint8_t device_feature[FEATURE_SIZE];
+	int mode = 0;/* there is 5 mode available, default is 0 */
+
+	saved_chip_number = this->current_chip;
+	nand->select_chip(mtd, 0);
+
+	/* [0] set proper timing */
+	__raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x1)
+			| BF_GPMI_TIMING0_DATA_HOLD(0x3)
+			| BF_GPMI_TIMING0_DATA_SETUP(0x3),
+			resources->gpmi_regs + HW_GPMI_TIMING0);
+
+	/* [1] send SET FEATURE commond to NAND */
+	memset(device_feature, 0, sizeof(device_feature));
+	device_feature[0] = (0x1 << 4) | (mode & 0x7);
+
+	nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	nand->cmdfunc(mtd, NAND_CMD_SET_FEATURE, 1, -1);
+	nand->write_buf(mtd, device_feature, FEATURE_SIZE);
+
+	/* [2] set clk divider */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN,
+			resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* [3] about the clock, pay attention! */
+	nand->select_chip(mtd, saved_chip_number);
+	{
+		struct clk *pll1;
+		pll1 = clk_get(NULL, "pll1_main_clk");
+		if (IS_ERR(pll1)) {
+			printk(KERN_INFO "No PLL1 clock\n");
+			return -EINVAL;
+		}
+		clk_set_parent(resources->clock, pll1);
+		clk_set_rate(resources->clock, 20000000);
+	}
+	nand->select_chip(mtd, 0);
+
+	/* [4] setup timing */
+	setup_ddr_timing_onfi(this);
+
+	/* [5] set to SYNC mode */
+	__raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE,
+			    resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+	__raw_writel(BM_GPMI_CTRL1_SSYNCMODE | BM_GPMI_CTRL1_GANGED_RDYBUSY,
+			    resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* common DDR initialization */
+	common_ddr_init(resources);
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	printk(KERN_INFO "Micron ONFI NAND enters synchronous mode %d\n", mode);
+	return 0;
+}
+
+static void setup_ddr_timing_toggle(struct gpmi_nand_data *this)
+{
+	uint32_t value;
+	struct resources  *resources = &this->resources;
+
+	/* set timing 2 register */
+	value = BF_GPMI_TIMING2_DATA_PAUSE(0x6)
+		| BF_GPMI_TIMING2_CMDADD_PAUSE(0x4)
+		| BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x3)
+		| BF_GPMI_TIMING2_PREAMBLE_DELAY(0x2)
+		| BF_GPMI_TIMING2_CE_DELAY(0x2)
+		| BF_GPMI_TIMING2_READ_LATENCY(0x2);
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2);
+
+	/* set timing 1 register */
+	__raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500),
+			resources->gpmi_regs + HW_GPMI_TIMING1);
+
+	/* Put GPMI in NAND mode, disable device reset, and make certain
+	   IRQRDY polarity is active high. */
+	value = BV_GPMI_CTRL1_GPMI_MODE__NAND
+		| BM_GPMI_CTRL1_GANGED_RDYBUSY
+		| (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3)
+		| (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2);
+
+	__raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+}
+
+static int enable_ddr_toggle(struct gpmi_nand_data *this)
+{
+	struct resources  *resources = &this->resources;
+	struct nand_chip *nand = &this->nand;
+	struct mtd_info	 *mtd = &this->mtd;
+	int saved_chip_number = this->current_chip;
+
+	nand->select_chip(mtd, 0);
+
+	/* [0] set proper timing */
+	__raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x5)
+			| BF_GPMI_TIMING0_DATA_HOLD(0xa)
+			| BF_GPMI_TIMING0_DATA_SETUP(0xa),
+			resources->gpmi_regs + HW_GPMI_TIMING0);
+
+	/* [2] set clk divider */
+	__raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN,
+			resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* [3] about the clock, pay attention! */
+	nand->select_chip(mtd, saved_chip_number);
+	{
+		struct clk *pll1;
+		unsigned long rate;
+
+		pll1 = clk_get(NULL, "pll1_main_clk");
+		if (IS_ERR(pll1)) {
+			printk(KERN_INFO "No PLL1 clock\n");
+			return -EINVAL;
+		}
+
+		/* toggle nand : 133/66 MHz */
+		rate = 33000000;
+		clk_set_parent(resources->clock, pll1);
+		clk_set_rate(resources->clock, rate);
+	}
+	nand->select_chip(mtd, 0);
+
+	/* [4] setup timing */
+	setup_ddr_timing_toggle(this);
+
+	/* [5] set to TOGGLE mode */
+	__raw_writel(BM_GPMI_CTRL1_SSYNCMODE,
+			    resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+	__raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE | BM_GPMI_CTRL1_GANGED_RDYBUSY,
+			    resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+	/* common DDR initialization */
+	common_ddr_init(resources);
+
+	nand->select_chip(mtd, saved_chip_number);
+
+	printk(KERN_INFO "-- Sumsung TOGGLE NAND is enabled now. --\n");
+	return 0;
+}
+
+inline bool is_board_support_ddr(struct gpmi_nand_data *this)
+{
+	 /* Only arm2 lpddr2pop board supports the DDR, */
+	 /* the common arm2 board does not. */
+	return this->pdata->enable_ddr;
+}
+
+inline bool is_ddr_nand(struct gpmi_nand_data *this)
+{
+	return this->nand.onfi_version;
+}
+
+/* To check if we need to initialize something else*/
+int extra_init(struct gpmi_nand_data *this)
+{
+	if (is_board_support_ddr(this)) {
+		if (1)
+			return enable_ddr_onfi(this);
+		if (0)
+			return enable_ddr_toggle(this);
+	}
+	return 0;
+}
+
 /*
  * Clear the bit and poll it cleared.  This is usually called with
  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
@@ -128,6 +407,12 @@ int gpmi_init(struct gpmi_nand_data *this)
 	struct resources *r = &this->resources;
 	int ret;
 
+	mxs_dma_clk = clk_get(NULL, "mxs-dma-apbh");
+	if (IS_ERR(mxs_dma_clk)) {
+		pr_err("can not get the dma clock\n");
+		ret = -ENOENT;
+		goto err_out;
+	}
 	ret = clk_prepare_enable(r->clock);
 	if (ret)
 		goto err_out;
@@ -224,11 +509,15 @@ int bch_set_geometry(struct gpmi_nand_data *this)
 	writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
 			| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
 			| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
+			| (is_ddr_nand(this) && is_board_support_ddr(this) ? \
+				BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 : 0)
 			| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
 			r->bch_regs + HW_BCH_FLASH0LAYOUT0);
 
 	writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
 			| BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
+			| (is_ddr_nand(this) && is_board_support_ddr(this) ? \
+				BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 : 0)
 			| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
 			r->bch_regs + HW_BCH_FLASH0LAYOUT1);
 
@@ -719,6 +1008,13 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		pr_err("We failed in enable the clk\n");
 		goto err_out;
 	}
+	if (!clk_get_usecount(mxs_dma_clk)) {
+		ret = clk_prepare_enable(mxs_dma_clk);
+		if (ret) {
+			pr_err("We failed in enable the dma clk\n");
+			goto err_out;
+		}
+	}
 
 	/* set ready/busy timeout */
 	writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
@@ -784,6 +1080,8 @@ void gpmi_end(struct gpmi_nand_data *this)
 {
 	struct resources *r = &this->resources;
 	clk_disable_unprepare(r->clock);
+	if (clk_get_usecount(mxs_dma_clk))
+		clk_disable_unprepare(mxs_dma_clk);
 }
 
 /* Clears a BCH interrupt. */
@@ -951,11 +1249,22 @@ int gpmi_send_page(struct gpmi_nand_data *this,
 	uint32_t address;
 	uint32_t ecc_command;
 	uint32_t buffer_mask;
+	uint32_t busw;
+	uint32_t page_size;
 	struct dma_async_tx_descriptor *desc;
 	struct dma_chan *channel = get_dma_chan(this);
 	int chip = this->current_chip;
 	u32 pio[6];
 
+	/* DDR use the 16-bit for DATA transmission! */
+	if (is_board_support_ddr(this) && is_ddr_nand(this)) {
+		busw		= BV_GPMI_CTRL0_WORD_LENGTH__16_BIT;
+		page_size	= geo->page_size >> 1;
+	} else {
+		busw		= BM_GPMI_CTRL0_WORD_LENGTH;
+		page_size	= geo->page_size;
+	}
+
 	/* A DMA descriptor that does an ECC page read. */
 	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
 	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
@@ -964,7 +1273,7 @@ int gpmi_send_page(struct gpmi_nand_data *this,
 				BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
 
 	pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
-		| BM_GPMI_CTRL0_WORD_LENGTH
+		| busw
 		| BF_GPMI_CTRL0_CS(chip, this)
 		| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
 		| BF_GPMI_CTRL0_ADDRESS(address)
@@ -973,7 +1282,7 @@ int gpmi_send_page(struct gpmi_nand_data *this,
 	pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
 		| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
 		| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
-	pio[3] = geo->page_size;
+	pio[3] = page_size;
 	pio[4] = payload;
 	pio[5] = auxiliary;
 
@@ -997,18 +1306,29 @@ int gpmi_read_page(struct gpmi_nand_data *this,
 	uint32_t address;
 	uint32_t ecc_command;
 	uint32_t buffer_mask;
+	uint32_t page_size;
+	uint32_t busw;
 	struct dma_async_tx_descriptor *desc;
 	struct dma_chan *channel = get_dma_chan(this);
 	int chip = this->current_chip;
 	unsigned long flags;
 	u32 pio[6];
 
+	/* DDR use the 16-bit for DATA transmission! */
+	if (is_board_support_ddr(this) && is_ddr_nand(this)) {
+		busw		= BV_GPMI_CTRL0_WORD_LENGTH__16_BIT;
+		page_size	= geo->page_size >> 1;
+	} else {
+		busw		= BM_GPMI_CTRL0_WORD_LENGTH;
+		page_size	= geo->page_size;
+	}
+
 	/* [1] Wait for the chip to report ready. */
 	command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
 	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 
 	pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
-		| BM_GPMI_CTRL0_WORD_LENGTH
+		| busw
 		| BF_GPMI_CTRL0_CS(chip, this)
 		| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
 		| BF_GPMI_CTRL0_ADDRESS(address)
@@ -1030,7 +1350,7 @@ int gpmi_read_page(struct gpmi_nand_data *this,
 			| BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
 
 	pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
-		| BM_GPMI_CTRL0_WORD_LENGTH
+		| busw
 		| BF_GPMI_CTRL0_CS(chip, this)
 		| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
 		| BF_GPMI_CTRL0_ADDRESS(address)
@@ -1040,7 +1360,7 @@ int gpmi_read_page(struct gpmi_nand_data *this,
 	pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
 		| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
 		| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
-	pio[3] = geo->page_size;
+	pio[3] = page_size;
 	pio[4] = payload;
 	pio[5] = auxiliary;
 
@@ -1061,11 +1381,11 @@ int gpmi_read_page(struct gpmi_nand_data *this,
 	address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 
 	pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
-		| BM_GPMI_CTRL0_WORD_LENGTH
+		| busw
 		| BF_GPMI_CTRL0_CS(chip, this)
 		| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
 		| BF_GPMI_CTRL0_ADDRESS(address)
-		| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
+		| BF_GPMI_CTRL0_XFER_COUNT(page_size);
 	pio[1] = 0;
 	pio[2] = 0; /* set GPMI_HW_GPMI_ECCCTRL, disable the BCH */
 	desc = channel->device->device_prep_slave_sg(channel,
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index ea3ce22ff9d5..f25b7c27b101 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -41,7 +41,30 @@ static struct nand_ecclayout gpmi_hw_ecclayout = {
 	.eccpos = { 0, },
 	.oobfree = { {.offset = 0, .length = 0} }
 };
+#if 0
+void gpmi_show_regs(struct gpmi_nand_data *this)
+{
+	struct resources *r = &this->resources;
+	u32 reg, bch;
+	int i;
+	int n;
+
+	n = 0xc0 / 0x10 + 1;
 
+	pr_info("-------------- Show GPMI registers ----------\n");
+	for (i = 0; i <= n; i++) {
+		reg = __raw_readl(r->gpmi_regs + i * 0x10);
+		pr_info("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
+	}
+	pr_info("-------------- Show GPMI registers end ----------\n");
+	pr_info("-------------- Show BCH registers ----------\n");
+	for (i = 0; i <= n; i++) {
+		reg = __raw_readl(r->bch_regs + i * 0x10);
+		pr_info("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
+	}
+	pr_info("-------------- Show BCH registers end ----------\n");
+}
+#endif
 static irqreturn_t bch_irq(int irq, void *cookie)
 {
 	struct gpmi_nand_data *this = cookie;
@@ -99,9 +122,14 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this)
 
 	/* The default for the length of Galois Field. */
 	geo->gf_len = 13;
+	if (is_ddr_nand(this) && is_board_support_ddr(this))
+		geo->gf_len = 14;
 
 	/* The default for chunk size. There is no oobsize greater then 512. */
 	geo->ecc_chunk_size = 512;
+	if (is_ddr_nand(this) && is_board_support_ddr(this))
+		geo->ecc_chunk_size = 1024;
+
 	while (geo->ecc_chunk_size < mtd->oobsize)
 		geo->ecc_chunk_size *= 2; /* keep C >= O */
 
@@ -115,6 +143,10 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this)
 	}
 
 	geo->page_size = mtd->writesize + mtd->oobsize;
+	if (is_ddr_nand(this) && is_board_support_ddr(this))
+		geo->page_size = mtd->writesize + geo->metadata_size
+			+ (geo->ecc_strength * geo->gf_len * 8
+			/ geo->ecc_chunk_count);
 	geo->payload_size = mtd->writesize;
 
 	/*
@@ -1001,6 +1033,19 @@ exit_auxiliary:
 	}
 }
 
+#define MAX_PAGESIZE 8192
+static uint8_t verify_buf[MAX_PAGESIZE];
+
+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
+{
+	struct nand_chip *nand = mtd->priv;
+
+	gpmi_ecc_read_page(mtd, nand, verify_buf, len);
+	if (memcmp(buf, verify_buf, len))
+		return -EFAULT;
+	return 0;
+}
+
 /*
  * There are several places in this driver where we have to handle the OOB and
  * block marks. This is the function where things are the most complicated, so
@@ -1401,6 +1446,25 @@ static int __devinit nand_boot_init(struct gpmi_nand_data  *this)
 	return 0;
 }
 
+#if 0
+static void show_nfc_geometry(struct bch_geometry *geo)
+{
+	pr_info("---------------------------------------\n");
+	pr_info("       NFC Geometry (used by BCH)\n");
+	pr_info("---------------------------------------\n");
+	pr_info("ECC Strength           : %u\n", geo->ecc_strength);
+	pr_info("Page Size in Bytes     : %u\n", geo->page_size);
+	pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size);
+	pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
+	pr_info("ECC Chunk Count        : %u\n", geo->ecc_chunk_count);
+	pr_info("Payload Size in Bytes  : %u\n", geo->payload_size);
+	pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
+	pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+	pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+	pr_info("Block Mark Bit Offset  : %u\n", geo->block_mark_bit_offset);
+}
+#endif
+
 static int __devinit gpmi_set_geometry(struct gpmi_nand_data *this)
 {
 	int ret;
@@ -1434,6 +1498,11 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
 	if (ret)
 		return ret;
 
+	/* extra init */
+	ret = extra_init(this);
+	if (ret != 0)
+		return ret;
+
 	/* NAND boot init, depends on the gpmi_set_geometry(). */
 	return nand_boot_init(this);
 }
@@ -1482,6 +1551,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 	chip->read_byte		= gpmi_read_byte;
 	chip->read_buf		= gpmi_read_buf;
 	chip->write_buf		= gpmi_write_buf;
+	chip->verify_buf	= gpmi_verify_buf;
 	chip->ecc.read_page	= gpmi_ecc_read_page;
 	chip->ecc.write_page	= gpmi_ecc_write_page;
 	chip->ecc.read_oob	= gpmi_ecc_read_oob;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 06a072bf85a1..229b2c5e1b12 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -235,6 +235,8 @@ struct timing_threshod {
 };
 
 /* Common Services */
+extern bool is_ddr_nand(struct gpmi_nand_data *);
+extern bool is_board_support_ddr(struct gpmi_nand_data *);
 extern int common_nfc_set_geometry(struct gpmi_nand_data *);
 extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
 extern void prepare_data_dma(struct gpmi_nand_data *,
@@ -245,6 +247,7 @@ extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
 				struct dma_async_tx_descriptor *);
 
 /* GPMI-NAND helper function library */
+extern int extra_init(struct gpmi_nand_data *);
 extern int gpmi_init(struct gpmi_nand_data *);
 extern void gpmi_clear_bch(struct gpmi_nand_data *);
 extern void gpmi_dump_info(struct gpmi_nand_data *);
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 83431240e2f2..a281716dc61a 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -1,7 +1,7 @@
 /*
  * Freescale GPMI NAND Flash Driver
  *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
  * Copyright 2008 Embedded Alley Solutions, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -108,32 +108,50 @@
 #define HW_GPMI_CTRL1_CLR				0x00000068
 #define HW_GPMI_CTRL1_TOG				0x0000006c
 
-#define BM_GPMI_CTRL1_BCH_MODE				(1 << 18)
-
-#define BP_GPMI_CTRL1_DLL_ENABLE			17
-#define BM_GPMI_CTRL1_DLL_ENABLE	(1 << BP_GPMI_CTRL1_DLL_ENABLE)
-
-#define BP_GPMI_CTRL1_HALF_PERIOD			16
-#define BM_GPMI_CTRL1_HALF_PERIOD	(1 << BP_GPMI_CTRL1_HALF_PERIOD)
-
-#define BP_GPMI_CTRL1_RDN_DELAY				12
-#define BM_GPMI_CTRL1_RDN_DELAY		(0xf << BP_GPMI_CTRL1_RDN_DELAY)
-#define BF_GPMI_CTRL1_RDN_DELAY(v)	\
-		(((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
-
-#define BM_GPMI_CTRL1_DEV_RESET				(1 << 3)
-#define BV_GPMI_CTRL1_DEV_RESET__ENABLED		0x0
-#define BV_GPMI_CTRL1_DEV_RESET__DISABLED		0x1
-
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY		(1 << 2)
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW	0x0
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH	0x1
-
-#define BM_GPMI_CTRL1_CAMERA_MODE			(1 << 1)
-#define BV_GPMI_CTRL1_GPMI_MODE__NAND			0x0
-#define BV_GPMI_CTRL1_GPMI_MODE__ATA			0x1
-
-#define BM_GPMI_CTRL1_GPMI_MODE				(1 << 0)
+#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000
+#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000
+#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000
+#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000
+#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000
+#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000
+#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000
+#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0
+#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1
+#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL      22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+	(((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1 0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD       16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY      12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)  \
+	(((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL      4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v)  \
+	(((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED  0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW  0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA  0x1
 
 #define HW_GPMI_TIMING0					0x00000070
 
@@ -154,8 +172,45 @@
 
 #define HW_GPMI_TIMING1					0x00000080
 #define BP_GPMI_TIMING1_BUSY_TIMEOUT			16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+	(((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
 
 #define HW_GPMI_TIMING2					0x00000090
+
+#define BP_GPMI_TIMING2_RSVD1      27
+#define BM_GPMI_TIMING2_RSVD1 0xF8000000
+#define BF_GPMI_TIMING2_RSVD1(v) \
+	(((v) << 27) & BM_GPMI_TIMING2_RSVD1)
+#define BP_GPMI_TIMING2_READ_LATENCY      24
+#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000
+#define BF_GPMI_TIMING2_READ_LATENCY(v)  \
+	(((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY)
+#define BP_GPMI_TIMING2_RSVD0      21
+#define BM_GPMI_TIMING2_RSVD0 0x00E00000
+#define BF_GPMI_TIMING2_RSVD0(v)  \
+	(((v) << 21) & BM_GPMI_TIMING2_RSVD0)
+#define BP_GPMI_TIMING2_CE_DELAY      16
+#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000
+#define BF_GPMI_TIMING2_CE_DELAY(v)  \
+	(((v) << 16) & BM_GPMI_TIMING2_CE_DELAY)
+#define BP_GPMI_TIMING2_PREAMBLE_DELAY      12
+#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000
+#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v)  \
+	(((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY)
+#define BP_GPMI_TIMING2_POSTAMBLE_DELAY      8
+#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00
+#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v)  \
+	(((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY)
+#define BP_GPMI_TIMING2_CMDADD_PAUSE      4
+#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0
+#define BF_GPMI_TIMING2_CMDADD_PAUSE(v)  \
+	(((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE)
+#define BP_GPMI_TIMING2_DATA_PAUSE      0
+#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F
+#define BF_GPMI_TIMING2_DATA_PAUSE(v)  \
+	(((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE)
+
 #define HW_GPMI_DATA					0x000000a0
 
 /* MX28 uses this to detect READY. */
@@ -169,4 +224,104 @@
 #define HW_GPMI_DEBUG					0x000000c0
 #define MX23_BP_GPMI_DEBUG_READY0			28
 #define MX23_BM_GPMI_DEBUG_READY0	(1 << MX23_BP_GPMI_DEBUG_READY0)
+
+#define HW_GPMI_READ_DDR_DLL_CTRL	(0x00000100)
+
+#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT      28
+#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000
+#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) \
+	(((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT)
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT      20
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v)  \
+	(((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT)
+#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1      18
+#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000
+#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v)  \
+	(((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1)
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL      10
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v)  \
+	(((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL)
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200
+#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100
+#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080
+#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET      3
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078
+#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v)  \
+	(((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET)
+#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004
+#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002
+#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001
+
+#define HW_GPMI_WRITE_DDR_DLL_CTRL	(0x00000110)
+
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT      28
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) \
+	(((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT      20
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v)  \
+	(((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1      18
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v)  \
+	(((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1)
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL      10
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v)  \
+	(((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL)
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080
+#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET      3
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078
+#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v)  \
+	(((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET)
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002
+#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001
+
+#define HW_GPMI_READ_DDR_DLL_STS	(0x00000120)
+
+#define BP_GPMI_READ_DDR_DLL_STS_RSVD1      25
+#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000
+#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) \
+	(((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1)
+#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL      17
+#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000
+#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v)  \
+	(((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL)
+#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000
+#define BP_GPMI_READ_DDR_DLL_STS_RSVD0      9
+#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00
+#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v)  \
+	(((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0)
+#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL      1
+#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE
+#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v)  \
+	(((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL)
+#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001
+
+#define HW_GPMI_WRITE_DDR_DLL_STS	(0x00000130)
+
+#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1      25
+#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000
+#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) \
+	(((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1)
+#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL      17
+#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000
+#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v)  \
+	(((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL)
+#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000
+#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0      9
+#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00
+#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v)  \
+	(((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0)
+#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL      1
+#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE
+#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v)  \
+	(((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL)
+#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001
 #endif
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
index c7d37df019ed..46a9645fcf25 100644
--- a/drivers/mxc/ipu3/ipu_device.c
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -371,13 +371,10 @@ static bool deinterlace_3_field(struct ipu_task_entry *t)
 
 static u32 tiled_filed_size(struct ipu_task_entry *t)
 {
-	u32 y_size;
 	u32 field_size;
 
 	/* note: page_align is required by VPU hw ouput buffer */
-	y_size = t->input.width * t->input.height/2;
-	field_size = ALIGN(y_size, SZ_4K) + ALIGN(y_size/2, SZ_4K);
-
+	field_size = TILED_NV12_FRAME_SIZE(t->input.width, t->input.height/2);
 	return field_size;
 }
 
diff --git a/drivers/mxc/ipu3/vdoa.c b/drivers/mxc/ipu3/vdoa.c
index 1a5266d7d7a8..2d3aaef16622 100644
--- a/drivers/mxc/ipu3/vdoa.c
+++ b/drivers/mxc/ipu3/vdoa.c
@@ -308,6 +308,7 @@ int vdoa_start(vdoa_handle_t handle, int timeout_ms)
 
 	CHECK_NULL_PTR(vdoa);
 	CHECK_STATE(VDOA_GET_OBUF, return -EINVAL);
+	vdoa->state = VDOA_START;
 	init_completion(&vdoa->comp);
 	vdoa_write_register(vdoa, VDOAIST,
 			VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
@@ -318,7 +319,6 @@ int vdoa_start(vdoa_handle_t handle, int timeout_ms)
 	vdoa_write_register(vdoa, VDOASRR, VDOASRR_START_XFER);
 	dump_registers(vdoa);
 
-	vdoa->state = VDOA_START;
 	ret = wait_for_completion_timeout(&vdoa->comp,
 			msecs_to_jiffies(timeout_ms));
 
diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
index 2051e8691a64..41470e954938 100644
--- a/drivers/rtc/rtc-snvs.c
+++ b/drivers/rtc/rtc-snvs.c
@@ -609,6 +609,9 @@ static int snvs_rtc_probe(struct platform_device *pdev)
 	tv.tv_nsec = 0;
 	tv.tv_sec = rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR);
 
+	/* Remove can_wakeup flag to add common power wakeup interface */
+	pdev->dev.power.can_wakeup = 0;
+
 	/* By default, devices should wakeup if they can */
 	/* So snvs is set as "should wakeup" as it can */
 	device_init_wakeup(&pdev->dev, 1);
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index eba760095956..be58e17dc526 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007, 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2008 Juergen Beisert
  *
  * This program is free software; you can redistribute it and/or
@@ -652,6 +652,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 	struct spi_imx_config config;
 
+	clk_enable(spi_imx->clk);
 	config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 	config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 	config.mode = spi->mode;
@@ -678,7 +679,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
 		BUG();
 
 	spi_imx->devtype_data.config(spi_imx, &config);
-
+	clk_disable(spi_imx->clk);
 	return 0;
 }
 
@@ -687,6 +688,7 @@ static int spi_imx_transfer(struct spi_device *spi,
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 
+	clk_enable(spi_imx->clk);
 	spi_imx->tx_buf = transfer->tx_buf;
 	spi_imx->rx_buf = transfer->rx_buf;
 	spi_imx->count = transfer->len;
@@ -699,6 +701,7 @@ static int spi_imx_transfer(struct spi_device *spi,
 	spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
 
 	wait_for_completion(&spi_imx->xfer_done);
+	clk_disable(spi_imx->clk);
 
 	return transfer->len;
 }
@@ -863,12 +866,12 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 	spi_imx->devtype_data.reset(spi_imx);
 
 	spi_imx->devtype_data.intctrl(spi_imx, 0);
-
 	ret = spi_bitbang_start(&spi_imx->bitbang);
 	if (ret) {
 		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
 		goto out_clk_put;
 	}
+	clk_disable(spi_imx->clk);
 
 	dev_info(&pdev->dev, "probed\n");
 
@@ -902,7 +905,7 @@ static int __devexit spi_imx_remove(struct platform_device *pdev)
 	int i;
 
 	spi_bitbang_stop(&spi_imx->bitbang);
-
+	clk_enable(spi_imx->clk);
 	writel(0, spi_imx->base + MXC_CSPICTRL);
 	clk_disable(spi_imx->clk);
 	clk_put(spi_imx->clk);
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index f8cd9bd076ce..d65c589cef60 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -881,7 +881,7 @@ static int imx_uart_dma_init(struct imx_port *sport)
 		goto err;
 	}
 
-	slave_config.direction = DMA_FROM_DEVICE;
+	slave_config.direction = DMA_DEV_TO_MEM;
 	slave_config.src_addr = sport->port.mapbase + URXD0;
 	slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 	slave_config.src_maxburst = RXTL; /* fix me */
@@ -908,7 +908,7 @@ static int imx_uart_dma_init(struct imx_port *sport)
 		goto err;
 	}
 
-	slave_config.direction = DMA_TO_DEVICE;
+	slave_config.direction = DMA_MEM_TO_DEV;
 	slave_config.dst_addr = sport->port.mapbase + URTX0;
 	slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 	slave_config.dst_maxburst = TXTL; /* fix me */
diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
index 5a1aab94b405..ea81802a3ca6 100755
--- a/drivers/usb/gadget/arcotg_udc.c
+++ b/drivers/usb/gadget/arcotg_udc.c
@@ -3458,7 +3458,11 @@ end:
 
 		dr_clk_gate(false);
 	}
-	--udc_controller->suspended;
+
+	if (!(--udc_controller->suspended) && !udc_controller->stopped) {
+		dr_clk_gate(true);
+		dr_phy_low_power_mode(udc_controller, false);
+	}
 	enable_irq(udc_controller->irq);
 	mutex_unlock(&udc_resume_mutex);
 	printk(KERN_DEBUG "USB Gadget resume ends\n");
diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h
index 00c8e8a8cdd7..8f4b88ebc283 100755
--- a/drivers/usb/gadget/arcotg_udc.h
+++ b/drivers/usb/gadget/arcotg_udc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -46,11 +46,7 @@
 #define NEED_IRAM(ep) ((g_iram_size) && \
 	((ep)->desc->bmAttributes == USB_ENDPOINT_XFER_BULK))
 
-#ifdef CONFIG_ARCH_MX5
 #define POSTPONE_FREE_LAST_DTD
-#else
-#undef POSTPONE_FREE_LAST_DTD
-#endif
 
 /* ### define USB registers here
  */
diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c
index 5bc048d216be..da77373e03a6 100644
--- a/drivers/video/mxc/mxc_epdc_fb.c
+++ b/drivers/video/mxc/mxc_epdc_fb.c
@@ -4726,9 +4726,15 @@ out_copybuffer:
 			      fb_data->phys_addr_copybuf);
 out_upd_buffers:
 	for (i = 0; i < fb_data->max_num_buffers; i++)
-		dma_free_writecombine(&pdev->dev, fb_data->max_pix_size,
-				      fb_data->virt_addr_updbuf[i],
-				      fb_data->phys_addr_updbuf[i]);
+		if (fb_data->virt_addr_updbuf[i] != NULL)
+			dma_free_writecombine(&pdev->dev,
+				fb_data->max_pix_size,
+				fb_data->virt_addr_updbuf[i],
+				fb_data->phys_addr_updbuf[i]);
+	if (fb_data->virt_addr_updbuf != NULL)
+		kfree(fb_data->virt_addr_updbuf);
+	if (fb_data->phys_addr_updbuf != NULL)
+		kfree(fb_data->phys_addr_updbuf);
 out_upd_lists:
 	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
 			list) {
@@ -4753,6 +4759,7 @@ static int mxc_epdc_fb_remove(struct platform_device *pdev)
 {
 	struct update_data_list *plist, *temp_list;
 	struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
+	int i;
 
 	mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
 
@@ -4766,6 +4773,16 @@ static int mxc_epdc_fb_remove(struct platform_device *pdev)
 	unregister_framebuffer(&fb_data->info);
 	free_irq(fb_data->epdc_irq, fb_data);
 
+	for (i = 0; i < fb_data->max_num_buffers; i++)
+		if (fb_data->virt_addr_updbuf[i] != NULL)
+			dma_free_writecombine(&pdev->dev, fb_data->max_pix_size,
+				fb_data->virt_addr_updbuf[i],
+				fb_data->phys_addr_updbuf[i]);
+	if (fb_data->virt_addr_updbuf != NULL)
+		kfree(fb_data->virt_addr_updbuf);
+	if (fb_data->phys_addr_updbuf != NULL)
+		kfree(fb_data->phys_addr_updbuf);
+
 	dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
 				fb_data->working_buffer_virt,
 				fb_data->working_buffer_phys);
@@ -4780,9 +4797,6 @@ static int mxc_epdc_fb_remove(struct platform_device *pdev)
 	list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
 			list) {
 		list_del(&plist->list);
-		dma_free_writecombine(&pdev->dev, fb_data->max_pix_size,
-				      plist->virt_addr,
-				      plist->phys_addr);
 		kfree(plist);
 	}
 #ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
diff --git a/drivers/video/mxc_hdmi.c b/drivers/video/mxc_hdmi.c
index 19d15df0d901..64a92316f974 100644
--- a/drivers/video/mxc_hdmi.c
+++ b/drivers/video/mxc_hdmi.c
@@ -570,6 +570,10 @@ static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
 	} else
 		return;
 
+	if (!hdmi->edid_cfg.vsd_dc_48bit && !hdmi->edid_cfg.vsd_dc_36bit &&
+		!hdmi->edid_cfg.vsd_dc_30bit && !hdmi->edid_cfg.vsd_dc_y444)
+		color_depth = 0;
+
 	/* set the packetizer registers */
 	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |