diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2013-03-20 16:03:06 -0700 |
|---|---|---|
| committer | Gabby Lee <galee@nvidia.com> | 2013-08-18 20:27:15 -0700 |
| commit | e313ddcbc64ed5095fa6b62b2a09c0724d799622 (patch) | |
| tree | 4ec70431fae17dd8dcf40065d83f7b136be8c5ea /drivers | |
| parent | bfa4af9fb1499f04fc56b45d31e31b4db17f2f86 (diff) | |
video: tegra: nvmap: enable iwb page pool if outer cache is present
If outer cache is not present, wb and iwb refer to same memory type
and page pool is not necessary.
Bug 1328248
Change-Id: I86713ccb4eb8d41b8129dd241dc72218039bbd26
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/259406
Reviewed-by: Harry Hong <hhong@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Gabby Lee <galee@nvidia.com>
Tested-by: Gabby Lee <galee@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/tegra/nvmap/nvmap_handle.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/video/tegra/nvmap/nvmap_handle.c b/drivers/video/tegra/nvmap/nvmap_handle.c index e0f3c630ca1a..d4b7a6087292 100644 --- a/drivers/video/tegra/nvmap/nvmap_handle.c +++ b/drivers/video/tegra/nvmap/nvmap_handle.c @@ -406,6 +406,16 @@ int nvmap_page_pool_init(struct nvmap_page_pool *pool, int flags) if (flags == NVMAP_HANDLE_CACHEABLE) return 0; +#if !defined(CONFIG_OUTER_CACHE) + /* If outer cache is not enabled or don't exist, cacheable and + * inner cacheable memory are same. For cacheable memory, there + * is no need of page pool as there is no need to flush cache and + * change page attributes. + */ + if (flags == NVMAP_HANDLE_INNER_CACHEABLE) + return 0; +#endif + si_meminfo(&info); if (!pool_size[flags] && !CONFIG_NVMAP_PAGE_POOL_SIZE) /* Use 3/8th of total ram for page pools. |