diff options
| author | Huang Shijie <b32955@freescale.com> | 2011-12-21 16:28:53 +0800 |
|---|---|---|
| committer | Huang Shijie <b32955@freescale.com> | 2011-12-26 14:22:58 +0800 |
| commit | f51432527ebcea1ec7097fc9a1ffae409b8b5f51 (patch) | |
| tree | 039979915fc53948c1ae2bbc631f4035a7d15093 /drivers | |
| parent | 8a168195d7f6b7f88a4f776f98fa7cc9ee93cf91 (diff) | |
ENGR00170901-1 IMX/UART : Revert "ENGR00170465-2"
This reverts commit 7e5181cd28ac3d786d0760f405fa5a1e3407a7a9.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/tty/serial/imx.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 8ebe2e81b332..76d593c31848 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -138,7 +138,6 @@ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RXTL_MASK 0x3f /* RX FIFO is 6 bits wide */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ @@ -191,8 +190,6 @@ #define UART_NR 8 -#define UART_RX_SIZE (16) - struct imx_port { struct uart_port port; struct timer_list timer; @@ -601,12 +598,6 @@ static void imx_dma_rxint(struct imx_port *sport) if ((temp & USR2_RDR) && !sport->dma_is_rxing) { sport->dma_is_rxing = true; - /* increase the RX FIFO threthold. */ - temp = readl(sport->port.membase + UFCR); - temp &= ~(UFCR_RXTL_MASK << UFCR_RXTL_SHF); - temp |= UART_RX_SIZE; - writel(temp, sport->port.membase + UFCR); - /* disable the `Recerver Ready Interrrupt` */ temp = readl(sport->port.membase + UCR1); temp &= ~(UCR1_RRDYEN); @@ -792,12 +783,6 @@ static void dma_rx_callback(void *data) temp |= UCR1_RRDYEN; writel(temp, sport->port.membase + UCR1); sport->dma_is_rxing = false; - - /* decrease the RX FIFO threthold. */ - temp = readl(sport->port.membase + UFCR); - temp &= ~(UFCR_RXTL_MASK << UFCR_RXTL_SHF); - temp |= RXTL; - writel(temp, sport->port.membase + UFCR); } } @@ -869,7 +854,7 @@ static int imx_uart_dma_init(struct imx_port *sport) slave_config.direction = DMA_FROM_DEVICE; slave_config.src_addr = sport->port.mapbase + URXD0; slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - slave_config.src_maxburst = UART_RX_SIZE; + slave_config.src_maxburst = RXTL; /* fix me */ ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); if (ret) { pr_err("error in RX dma configuration.\n"); |