diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-07-18 13:46:15 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-07-18 13:46:15 -0700 |
| commit | df57a12e5bdaa0b5ab0ce0d8a9d50933835c4de8 (patch) | |
| tree | 35a3b51ceec36f1a45f6b31729e2fb03887bc047 /drivers | |
| parent | eb479e52f9c6d32164ae76606fd7ce372f2aa153 (diff) | |
| parent | 77f61547834c4f127b44b13e43c59133a35880dc (diff) | |
Merge remote-tracking branch 'nxp/imx_4.1.15_1.0.0_ga' into toradex_imx_4.1.15_1.0.0_ga-next
Diffstat (limited to 'drivers')
22 files changed, 771 insertions, 517 deletions
diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c index de679b06945c..0128881a1690 100644 --- a/drivers/dma/pxp/pxp_dma_v2.c +++ b/drivers/dma/pxp/pxp_dma_v2.c @@ -1125,11 +1125,10 @@ static void pxp_clk_disable(struct pxps *pxp) if (pxp->clk_disp_axi) clk_disable_unprepare(pxp->clk_disp_axi); pxp->clk_stat = CLK_STAT_OFF; + pm_runtime_put_sync_suspend(pxp->dev); } else spin_unlock_irqrestore(&pxp->lock, flags); - pm_runtime_put_sync_suspend(pxp->dev); - mutex_unlock(&pxp->clk_mutex); } diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c index f44045084958..085f1aad4b74 100644 --- a/drivers/dma/pxp/pxp_dma_v3.c +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -87,7 +87,8 @@ struct pxp_dma { struct pxps { struct platform_device *pdev; - struct clk *clk; + struct clk *ipg_clk; + struct clk *axi_clk; void __iomem *base; int irq; /* PXP IRQ to the CPU */ @@ -1276,7 +1277,8 @@ static void pxp_clk_enable(struct pxps *pxp) pm_runtime_get_sync(pxp->dev); - clk_prepare_enable(pxp->clk); + clk_prepare_enable(pxp->ipg_clk); + clk_prepare_enable(pxp->axi_clk); pxp->clk_stat = CLK_STAT_ON; mutex_unlock(&pxp->clk_mutex); @@ -1296,7 +1298,8 @@ static void pxp_clk_disable(struct pxps *pxp) spin_lock_irqsave(&pxp->lock, flags); if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { spin_unlock_irqrestore(&pxp->lock, flags); - clk_disable_unprepare(pxp->clk); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); pxp->clk_stat = CLK_STAT_OFF; } else spin_unlock_irqrestore(&pxp->lock, flags); @@ -1809,6 +1812,8 @@ static void pxp_issue_pending(struct dma_chan *chan) struct pxps *pxp = to_pxp(pxp_dma); unsigned long flags0, flags; + down(&pxp->sema); + spin_lock_irqsave(&pxp->lock, flags0); spin_lock_irqsave(&pxp_chan->lock, flags); @@ -1825,7 +1830,6 @@ static void pxp_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&pxp->lock, flags0); pxp_clk_enable(pxp); - down(&pxp->sema); spin_lock_irqsave(&pxp->lock, flags); pxp->pxp_ongoing = 1; @@ -4310,7 +4314,14 @@ static int pxp_probe(struct platform_device *pdev) pxp->pdev = pdev; - pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); + pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); + pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); + + if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { + dev_err(&pdev->dev, "pxp clocks invalid\n"); + err = -EINVAL; + goto exit; + } err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, "pxp-dmaengine", pxp); @@ -4385,7 +4396,8 @@ static int pxp_remove(struct platform_device *pdev) unregister_pxp_device(); cancel_work_sync(&pxp->work); del_timer_sync(&pxp->clk_timer); - clk_disable_unprepare(pxp->clk); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); device_remove_file(&pdev->dev, &dev_attr_block_size); dma_async_device_unregister(&(pxp->pxp_dma.dma)); diff --git a/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c b/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c index 17f3c07fa8a4..b3bc18125359 100644 --- a/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c +++ b/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c @@ -106,7 +106,7 @@ static unsigned int v4l2_fmt_to_pxp_fmt(u32 v4l2_pix_fmt) u32 pxp_fmt = 0; if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB24) - pxp_fmt = PXP_PIX_FMT_RGB24; + pxp_fmt = PXP_PIX_FMT_RGB32; else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB565) pxp_fmt = PXP_PIX_FMT_RGB565; else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555) @@ -478,7 +478,7 @@ static int pxp_s_output(struct file *file, void *fh, pxp->pxp_conf.out_param.width = fmt->width; pxp->pxp_conf.out_param.height = fmt->height; if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) - pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB24; + pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB32; else pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB565; diff --git a/drivers/media/platform/mxc/subdev/mx6s_capture.c b/drivers/media/platform/mxc/subdev/mx6s_capture.c index ed60f8dc72dd..49d4f73c4c24 100644 --- a/drivers/media/platform/mxc/subdev/mx6s_capture.c +++ b/drivers/media/platform/mxc/subdev/mx6s_capture.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -588,33 +588,7 @@ static void csi_dmareq_rff_disable(struct mx6s_csi_dev *csi_dev) __raw_writel(cr3, csi_dev->regbase + CSI_CSICR3); } -static void csi_set_32bit_imagpara(struct mx6s_csi_dev *csi, - int width, int height) -{ - int imag_para = 0; - unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3); - - imag_para = (width << 16) | height; - __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA); - - /* reflash the embeded DMA controller */ - __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3); -} - -static void csi_set_16bit_imagpara(struct mx6s_csi_dev *csi, - int width, int height) -{ - int imag_para = 0; - unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3); - - imag_para = ((width * 2) << 16) | height; - __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA); - - /* reflash the embeded DMA controller */ - __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3); -} - -static void csi_set_8bit_imagpara(struct mx6s_csi_dev *csi, +static void csi_set_imagpara(struct mx6s_csi_dev *csi, int width, int height) { int imag_para = 0; @@ -816,6 +790,7 @@ static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev) { struct v4l2_pix_format *pix = &csi_dev->pix; u32 cr1, cr18; + u32 width; if (pix->field == V4L2_FIELD_INTERLACED) { csi_deinterlace_enable(csi_dev, true); @@ -828,21 +803,22 @@ static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev) switch (csi_dev->fmt->pixelformat) { case V4L2_PIX_FMT_YUV32: - csi_set_32bit_imagpara(csi_dev, pix->width, pix->height); + case V4L2_PIX_FMT_SBGGR8: + width = pix->width; break; case V4L2_PIX_FMT_UYVY: - csi_set_16bit_imagpara(csi_dev, pix->width, pix->height); - break; case V4L2_PIX_FMT_YUYV: - csi_set_16bit_imagpara(csi_dev, pix->width, pix->height); - break; - case V4L2_PIX_FMT_SBGGR8: - csi_set_8bit_imagpara(csi_dev, pix->width, pix->height); + if (csi_dev->csi_mux_mipi == true) + width = pix->width; + else + /* For parallel 8-bit sensor input */ + width = pix->width * 2; break; default: pr_debug(" case not supported\n"); return -EINVAL; } + csi_set_imagpara(csi_dev, width, pix->height); if (csi_dev->csi_mux_mipi == true) { cr1 = csi_read(csi_dev, CSI_CSICR1); diff --git a/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c b/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c index a1ed48a9507a..bb9dd3d48e53 100644 --- a/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c +++ b/drivers/media/platform/mxc/subdev/mxc_mipi_csi.c @@ -1,7 +1,7 @@ /* * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver * - * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -250,6 +250,7 @@ struct csis_hw_reset { * @flags: the state variable for power and streaming control * @clock_frequency: device bus clock frequency * @hs_settle: HS-RX settle time + * @clk_settle: Clk settle time * @num_lanes: number of MIPI-CSI data lanes used * @max_num_lanes: maximum number of MIPI-CSI data lanes supported * @wclk_ext: CSI wrapper clock: 0 - bus clock, 1 - external SCLK_CAM @@ -277,6 +278,7 @@ struct csi_state { u32 clk_frequency; u32 hs_settle; + u32 clk_settle; u32 num_lanes; u32 max_num_lanes; u8 wclk_ext; @@ -379,11 +381,6 @@ static int mipi_csis_phy_init(struct csi_state *state) ret = regulator_set_voltage(state->mipi_phy_regulator, 1000000, 1000000); - ret = regulator_enable(state->mipi_phy_regulator); - if (ret) { - dev_err(state->dev, "failed to set mipi regulator.\n"); - return ret; - } return ret; } @@ -468,11 +465,14 @@ static void __mipi_csis_set_format(struct csi_state *state) mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); } -static void mipi_csis_set_hsync_settle(struct csi_state *state, int settle) +static void mipi_csis_set_hsync_settle(struct csi_state *state, + int hs_settle, int clk_settle) { u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); - val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (settle << 24); + val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | + (hs_settle << 24) | (clk_settle << 22); + mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); } @@ -487,7 +487,7 @@ static void mipi_csis_set_params(struct csi_state *state) __mipi_csis_set_format(state); - mipi_csis_set_hsync_settle(state, state->hs_settle); + mipi_csis_set_hsync_settle(state, state->hs_settle, state->clk_settle); val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0); if (state->csis_fmt->data_alignment == 32) @@ -942,6 +942,9 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, /* Get MIPI CSI-2 bus configration from the endpoint node. */ of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); + + of_property_read_u32(node, "csis-clk-settle", + &state->clk_settle); state->wclk_ext = of_property_read_bool(node, "csis-wclk"); @@ -1117,9 +1120,10 @@ static int mipi_csis_probe(struct platform_device *pdev) goto e_sd_host; } - dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n", - state->num_lanes, state->hs_settle, state->wclk_ext, - state->clk_frequency); + dev_info(&pdev->dev, + "lanes: %d, hs_settle: %d, clk_settle: %d, wclk: %d, freq: %u\n", + state->num_lanes, state->hs_settle, state->clk_settle, + state->wclk_ext, state->clk_frequency); return 0; e_sd_host: diff --git a/drivers/media/platform/mxc/subdev/ov5640_mipi.c b/drivers/media/platform/mxc/subdev/ov5640_mipi.c index 135eefa550a7..739a24c7d426 100644 --- a/drivers/media/platform/mxc/subdev/ov5640_mipi.c +++ b/drivers/media/platform/mxc/subdev/ov5640_mipi.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -44,15 +44,11 @@ enum ov5640_mode { ov5640_mode_MIN = 0, ov5640_mode_VGA_640_480 = 0, - ov5640_mode_QVGA_320_240 = 1, - ov5640_mode_NTSC_720_480 = 2, - ov5640_mode_PAL_720_576 = 3, - ov5640_mode_720P_1280_720 = 4, - ov5640_mode_1080P_1920_1080 = 5, - ov5640_mode_QSXGA_2592_1944 = 6, - ov5640_mode_QCIF_176_144 = 7, - ov5640_mode_XGA_1024_768 = 8, - ov5640_mode_MAX = 8, + ov5640_mode_NTSC_720_480 = 1, + ov5640_mode_720P_1280_720 = 2, + ov5640_mode_1080P_1920_1080 = 3, + ov5640_mode_QSXGA_2592_1944 = 4, + ov5640_mode_MAX = 5, ov5640_mode_INIT = 0xff, /*only for sensor init*/ }; @@ -212,55 +208,12 @@ static struct reg_value ov5640_init_setting_30fps_VGA[] = { {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, - {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300}, + {0x3a1f, 0x14, 0, 0}, {0x3008, 0x42, 0, 0}, {0x3c00, 0x04, 0, 300}, }; static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { - - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_VGA_640_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { - - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, + {0x3008, 0x42, 0, 0}, + {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -277,117 +230,12 @@ static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, - {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, - {0x380b, 0x00, 0, 0}, {0x3035, 0x12, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3808, 0x04, 0, 0}, - {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; -static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, - {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, + {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0x00, 0, 0}, }; static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { + {0x3008, 0x42, 0, 0}, {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, @@ -406,69 +254,7 @@ static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, - {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_30fps_PAL_720_576[] = { - {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static struct reg_value ov5640_setting_15fps_PAL_720_576[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, - {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, + {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, }; static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { @@ -494,27 +280,6 @@ static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, }; -static struct reg_value ov5640_setting_15fps_720P_1280_720[] = { - {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, - {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, - {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, - {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, - {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, - {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, - {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, - {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, -}; - static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3008, 0x42, 0, 0}, {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, @@ -552,43 +317,8 @@ static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3503, 0, 0, 0}, }; -static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = { - {0x3008, 0x42, 0, 0}, - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, - {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, - {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, - {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, - {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, - {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0}, - {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, - {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, - {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0}, - {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, - {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0}, - {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, - {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, - {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, - {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, - {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, - {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, -}; - static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { + {0x3008, 0x42, 0, 0}, {0x4202, 0x0f, 0, 0}, /* stream off the sensor */ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, /*disable flip*/ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, @@ -608,53 +338,27 @@ static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70}, + {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70}, {0x3008, 0x02, 0, 0}, {0x4202, 0x00, 0, 0}, /* stream on the sensor */ }; static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { { - {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, - ov5640_setting_15fps_VGA_640_480, - ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)}, - {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, - ov5640_setting_15fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)}, - {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, - ov5640_setting_15fps_NTSC_720_480, - ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)}, - {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, - ov5640_setting_15fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)}, - {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, - ov5640_setting_15fps_720P_1280_720, - ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)}, - {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080, - ov5640_setting_15fps_1080P_1920_1080, - ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)}, + {ov5640_mode_VGA_640_480, -1, 0, 0, NULL, 0}, + {ov5640_mode_NTSC_720_480, -1, 0, 0, NULL, 0}, + {ov5640_mode_720P_1280_720, -1, 0, 0, NULL, 0}, + {ov5640_mode_1080P_1920_1080, -1, 0, 0, NULL, 0}, {ov5640_mode_QSXGA_2592_1944, SCALING, 2592, 1944, ov5640_setting_15fps_QSXGA_2592_1944, ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, - {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, - ov5640_setting_15fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)}, - {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, - ov5640_setting_15fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)}, }, { {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, ov5640_setting_30fps_VGA_640_480, ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, - {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, - ov5640_setting_30fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, ov5640_setting_30fps_NTSC_720_480, ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, - {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, - ov5640_setting_30fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, ov5640_setting_30fps_720P_1280_720, ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, @@ -662,12 +366,6 @@ static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { ov5640_setting_30fps_1080P_1920_1080, ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)}, {ov5640_mode_QSXGA_2592_1944, -1, 0, 0, NULL, 0}, - {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, - ov5640_setting_30fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)}, - {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, - ov5640_setting_30fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)}, }, }; @@ -724,17 +422,22 @@ static const struct ov5640_datafmt static inline void ov5640_power_down(int enable) { - /* 19x19 pwdn pin invert by mipi daughter card */ + if (pwn_gpio < 0) + return; + if (!enable) - gpio_set_value(pwn_gpio, 1); + gpio_set_value_cansleep(pwn_gpio, 0); else - gpio_set_value(pwn_gpio, 0); + gpio_set_value_cansleep(pwn_gpio, 1); msleep(2); } static void ov5640_reset(void) { + if (rst_gpio < 0 || pwn_gpio < 0) + return; + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -869,6 +572,7 @@ static void OV5640_stream_on(void) static void OV5640_stream_off(void) { ov5640_write_reg(0x4202, 0x0f); + ov5640_write_reg(0x3008, 0x42); } static int OV5640_get_sysclk(void) @@ -1402,12 +1106,9 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, /* dump the first two frames: 1/7.5*2 * the frame rate of QSXGA is 7.5fps */ msec_wait4stable = 267; - } else if (frame_rate == ov5640_15_fps) { - /* dump the first nine frames: 1/15*9 */ + } else { + /* dump the first eighteen frames: 1/30*18 */ msec_wait4stable = 600; - } else if (frame_rate == ov5640_30_fps) { - /* dump the first nine frames: 1/30*9 */ - msec_wait4stable = 300; } msleep(msec_wait4stable); @@ -1808,31 +1509,35 @@ static int ov5640_probe(struct i2c_client *client, /* ov5640 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); - if (IS_ERR(pinctrl)) { - dev_warn(dev, "no pin available\n"); - } + if (IS_ERR(pinctrl)) + dev_warn(dev, "no pin available\n"); /* request power down pin */ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); - if (!gpio_is_valid(pwn_gpio)) { + if (!gpio_is_valid(pwn_gpio)) dev_warn(dev, "no sensor pwdn pin available"); - return -EINVAL; + else { + retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } } - retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, - "ov5640_mipi_pwdn"); - if (retval < 0) - return retval; /* request reset pin */ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); - if (!gpio_is_valid(rst_gpio)) { + if (!gpio_is_valid(rst_gpio)) dev_warn(dev, "no sensor reset pin available"); - return -EINVAL; + else { + retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } } - retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, - "ov5640_mipi_reset"); - if (retval < 0) - return retval; /* Set initial values for the sensor struct. */ memset(&ov5640_data, 0, sizeof(ov5640_data)); @@ -1913,6 +1618,7 @@ static int ov5640_probe(struct i2c_client *client, dev_err(&client->dev, "%s--Async register failed, ret=%d\n", __func__, retval); + OV5640_stream_off(); pr_info("camera ov5640_mipi is found\n"); return retval; } diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 6a50cc6faf72..cd5280f686d7 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -489,6 +489,7 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value, unsigned long timeout; u32 status = 0; bool use_r1b_resp = use_busy_signal; + bool expired = false; mmc_retune_hold(host); @@ -548,9 +549,15 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value, timeout_ms = MMC_OPS_TIMEOUT_MS; /* Must check status to be sure of no errors. */ - timeout = jiffies + msecs_to_jiffies(timeout_ms); + timeout = jiffies + msecs_to_jiffies(timeout_ms) + 1; do { if (send_status) { + /* + * Due to the possibility of being preempted after + * sending the status command, check the expiration + * time first. + */ + expired = time_after(jiffies, timeout); err = __mmc_send_status(card, &status, ignore_crc); if (err) goto out; @@ -571,7 +578,7 @@ int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value, } /* Timeout if the device never leaves the program state. */ - if (time_after(jiffies, timeout)) { + if (expired && R1_CURRENT_STATE(status) == R1_STATE_PRG) { pr_err("%s: Card stuck in programming state! %s\n", mmc_hostname(host), __func__); err = -ETIMEDOUT; diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index b5293f36d45d..e3807494979a 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" +#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f #define ESDHC_CTRL_D3CD 0x08 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) /* VENDOR SPEC register */ @@ -140,8 +141,6 @@ #define ESDHC_FLAG_HS200 BIT(8) /* The IP supports HS400 mode */ #define ESDHC_FLAG_HS400 BIT(9) -/* need request bus freq during low power */ -#define ESDHC_FLAG_BUSFREQ BIT(10) /* A higher clock ferquency than this rate requires strobell dll control */ #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 @@ -186,7 +185,7 @@ static struct esdhc_soc_data usdhc_imx6q_data = { static struct esdhc_soc_data usdhc_imx6sl_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 - | ESDHC_FLAG_HS200 | ESDHC_FLAG_BUSFREQ, + | ESDHC_FLAG_HS200, }; static struct esdhc_soc_data usdhc_imx6sx_data = { @@ -990,7 +989,7 @@ static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = pltfm_host->priv; - return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; + return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; } static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) @@ -999,7 +998,8 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) struct pltfm_imx_data *imx_data = pltfm_host->priv; /* use maximum timeout counter */ - sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, + esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, + esdhc_is_usdhc(imx_data) ? 0xF : 0xE, SDHCI_TIMEOUT_CONTROL); } @@ -1217,8 +1217,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) pltfm_host->clk = imx_data->clk_per; pltfm_host->clock = clk_get_rate(pltfm_host->clk); - if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ) - request_bus_freq(BUS_FREQ_HIGH); + request_bus_freq(BUS_FREQ_HIGH); clk_prepare_enable(imx_data->clk_per); clk_prepare_enable(imx_data->clk_ipg); @@ -1310,8 +1309,7 @@ disable_clk: clk_disable_unprepare(imx_data->clk_per); clk_disable_unprepare(imx_data->clk_ipg); clk_disable_unprepare(imx_data->clk_ahb); - if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ) - release_bus_freq(BUS_FREQ_HIGH); + release_bus_freq(BUS_FREQ_HIGH); free_sdhci: sdhci_pltfm_free(pdev); return err; @@ -1355,8 +1353,7 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev) } clk_disable_unprepare(imx_data->clk_ahb); - if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ) - release_bus_freq(BUS_FREQ_HIGH); + release_bus_freq(BUS_FREQ_HIGH); return ret; } @@ -1367,8 +1364,7 @@ static int sdhci_esdhc_runtime_resume(struct device *dev) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = pltfm_host->priv; - if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ) - request_bus_freq(BUS_FREQ_HIGH); + request_bus_freq(BUS_FREQ_HIGH); if (!sdhci_sdio_irq_enabled(host)) { clk_prepare_enable(imx_data->clk_per); diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index b72e5f68ac7a..8339d4fd4ddd 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -559,9 +559,11 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this) return -EINVAL; } - if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && - !(mtd->oobsize > 1024)) + if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && + (mtd->oobsize < 1024)) || this->legacy_bch_geometry) { + dev_warn(this->dev, "use legacy bch geometry\n"); return legacy_set_geometry(this); + } if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize) return set_geometry_for_large_oob(this); @@ -1008,6 +1010,7 @@ static void gpmi_free_dma_buffer(struct gpmi_nand_data *this) this->cmd_buffer = NULL; this->data_buffer_dma = NULL; + this->raw_buffer = NULL; this->page_buffer_virt = NULL; this->page_buffer_size = 0; } @@ -2114,7 +2117,7 @@ static int mx23_boot_init(struct gpmi_nand_data *this) */ chipnr = block >> (chip->chip_shift - chip->phys_erase_shift); page = block << (chip->phys_erase_shift - chip->page_shift); - byte = block << chip->phys_erase_shift; + byte = (loff_t) block << chip->phys_erase_shift; /* Send the command to read the conventional block mark. */ chip->select_chip(mtd, chipnr); @@ -2262,6 +2265,9 @@ static int gpmi_nand_init(struct gpmi_nand_data *this) if (of_get_nand_on_flash_bbt(this->dev->of_node)) { chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; + if (of_property_read_bool(this->dev->of_node, + "fsl,legacy-bch-geometry")) + this->legacy_bch_geometry = true; if (of_property_read_bool(this->dev->of_node, "fsl,no-blockmark-swap")) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index c3a51f1bb143..a92158ad29e8 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h @@ -197,6 +197,8 @@ struct gpmi_nand_data { dma_addr_t auxiliary_phys; void *raw_buffer; + /* legacy bch geometry flag */ + bool legacy_bch_geometry; /* DMA channels */ #define DMA_CHANS 8 diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c index b78fb65e2246..f7d31bf0acb9 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c @@ -576,6 +576,8 @@ gceSTATUS gckVGKERNEL_Dispatch( gckVIDMEM_HANDLE_Lookup(Kernel, processID, (gctUINT32)kernelInterface->u.ReleaseVideoMemory.node, &nodeObject)); + gckVIDMEM_HANDLE_Dereference(Kernel, processID,(gctUINT32)Interface->u.ReleaseVideoMemory.node); + gckVIDMEM_NODE_Dereference(Kernel, nodeObject); } diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index f3644cf4aa3a..9613856e3a09 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -1,7 +1,7 @@ /* * Core driver for the imx pin controller * - * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng <dong.aisheng@linaro.org> @@ -485,13 +485,6 @@ static const struct pinconf_ops imx_pinconf_ops = { .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, }; -static struct pinctrl_desc imx_pinctrl_desc = { - .pctlops = &imx_pctrl_ops, - .pmxops = &imx_pmx_ops, - .confops = &imx_pinconf_ops, - .owner = THIS_MODULE, -}; - /* * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and * 1 u32 CONFIG, so 24 types in total for each pin. @@ -659,6 +652,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, struct device_node *np; struct imx_pinctrl *ipctl; struct resource *res; + struct pinctrl_desc *imx_pinctrl_desc; int ret, i; if (!info || !info->pins || !info->npins) { @@ -667,6 +661,11 @@ int imx_pinctrl_probe(struct platform_device *pdev, } info->dev = &pdev->dev; + imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), + GFP_KERNEL); + if (!imx_pinctrl_desc) + return -ENOMEM; + /* Create state holders etc for this driver */ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); if (!ipctl) @@ -704,9 +703,13 @@ int imx_pinctrl_probe(struct platform_device *pdev, of_node_put(np); } - imx_pinctrl_desc.name = dev_name(&pdev->dev); - imx_pinctrl_desc.pins = info->pins; - imx_pinctrl_desc.npins = info->npins; + imx_pinctrl_desc->name = dev_name(&pdev->dev); + imx_pinctrl_desc->pins = info->pins; + imx_pinctrl_desc->npins = info->npins; + imx_pinctrl_desc->pctlops = &imx_pctrl_ops; + imx_pinctrl_desc->pmxops = &imx_pmx_ops; + imx_pinctrl_desc->confops = &imx_pinconf_ops; + imx_pinctrl_desc->owner = THIS_MODULE; ret = imx_pinctrl_probe_dt(pdev, info); if (ret) { @@ -717,7 +720,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, ipctl->info = info; ipctl->dev = info->dev; platform_set_drvdata(pdev, ipctl); - ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); + ipctl->pctl = pinctrl_register(imx_pinctrl_desc, &pdev->dev, ipctl); if (!ipctl->pctl) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); return -EINVAL; diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c index 0e59c812fc0b..b1ba565af1ba 100644 --- a/drivers/usb/chipidea/ci_hdrc_imx.c +++ b/drivers/usb/chipidea/ci_hdrc_imx.c @@ -1,5 +1,5 @@ /* - * Copyright 2012-2015 Freescale Semiconductor, Inc. + * Copyright 2012-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Marek Vasut <marex@denx.de> * on behalf of DENX Software Engineering GmbH * @@ -136,10 +136,15 @@ static inline bool is_imx6sx_con(struct ci_hdrc_imx_data *imx_data) return imx_data->data == &imx6sx_usb_data; } +static inline bool is_imx7d_con(struct ci_hdrc_imx_data *imx_data) +{ + return imx_data->data == &imx7d_usb_data; +} + static inline bool imx_has_hsic_con(struct ci_hdrc_imx_data *imx_data) { return is_imx6q_con(imx_data) || is_imx6sl_con(imx_data) - || is_imx6sx_con(imx_data); + || is_imx6sx_con(imx_data) || is_imx7d_con(imx_data); } /* Common functions shared by usbmisc drivers */ diff --git a/drivers/usb/chipidea/host.h b/drivers/usb/chipidea/host.h index 527c9607b2ba..4dfb59a05a1a 100644 --- a/drivers/usb/chipidea/host.h +++ b/drivers/usb/chipidea/host.h @@ -20,7 +20,7 @@ static inline void ci_hdrc_host_destroy(struct ci_hdrc *ci) } -static void ci_hdrc_host_driver_init(void) +static inline void ci_hdrc_host_driver_init(void) { } diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c index 43c6ec29d825..5f133fb2ca6d 100644 --- a/drivers/usb/chipidea/usbmisc_imx.c +++ b/drivers/usb/chipidea/usbmisc_imx.c @@ -381,7 +381,7 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) { struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev); unsigned long flags; - u32 reg; + u32 reg, val; if (data->index > 3) return -EINVAL; @@ -399,6 +399,27 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data) writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc->base + data->index * 4); + /* For HSIC controller */ + if (data->index == 2 || data->index == 3) { + val = readl(usbmisc->base + data->index * 4); + writel(val | MX6_BM_UTMI_ON_CLOCK, + usbmisc->base + data->index * 4); + val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON; + writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + + (data->index - 2) * 4); + + /* + * Need to add delay to wait 24M OSC to be stable, + * It is board specific. + */ + regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); + /* 0 <= data->osc_clkgate_delay <= 7 */ + if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) + regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, + (data->osc_clkgate_delay) << 26); + } spin_unlock_irqrestore(&usbmisc->lock, flags); usbmisc_imx6q_set_wakeup(data, false); @@ -415,9 +436,9 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) usbmisc_imx6q_init(data); + spin_lock_irqsave(&usbmisc->lock, flags); if (data->index == 0 || data->index == 1) { reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; - spin_lock_irqsave(&usbmisc->lock, flags); /* Set vbus wakeup source as bvalid */ val = readl(reg); writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); @@ -428,33 +449,17 @@ static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data) val = readl(usbmisc->base + data->index * 4); writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN, usbmisc->base + data->index * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); } /* For HSIC controller */ if (data->index == 2) { - spin_lock_irqsave(&usbmisc->lock, flags); - val = readl(usbmisc->base + data->index * 4); - writel(val | MX6_BM_UTMI_ON_CLOCK, - usbmisc->base + data->index * 4); val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON | - MX6SX_BM_HSIC_AUTO_RESUME; + val |= MX6SX_BM_HSIC_AUTO_RESUME; writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + (data->index - 2) * 4); - spin_unlock_irqrestore(&usbmisc->lock, flags); - - /* - * Need to add delay to wait 24M OSC to be stable, - * it's board specific. - */ - regmap_read(data->anatop, ANADIG_ANA_MISC0, &val); - /* 0 <= data->osc_clkgate_delay <= 7 */ - if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val)) - regmap_write(data->anatop, ANADIG_ANA_MISC0_SET, - (data->osc_clkgate_delay) << 26); } + spin_unlock_irqrestore(&usbmisc->lock, flags); return 0; } diff --git a/drivers/video/fbdev/mxc/Kconfig b/drivers/video/fbdev/mxc/Kconfig index 801da762ff34..3650a538d5ff 100644 --- a/drivers/video/fbdev/mxc/Kconfig +++ b/drivers/video/fbdev/mxc/Kconfig @@ -33,6 +33,16 @@ config FB_MXC_TRULY_WVGA_SYNC_PANEL depends on FB_MXC_SYNC_PANEL depends on FB_MXC_MIPI_DSI || FB_MXC_MIPI_DSI_SAMSUNG +config FB_MXC_TRULY_PANEL_TFT3P5079E + tristate "TRULY Panel TFT3P5079E" + depends on FB_MXC_SYNC_PANEL + depends on FB_MXC_MIPI_DSI_SAMSUNG + +config FB_MXC_TRULY_PANEL_TFT3P5581E + tristate "TRULY Panel TFT3P5581E" + depends on FB_MXC_SYNC_PANEL + depends on FB_MXC_MIPI_DSI_SAMSUNG + config FB_MXC_LDB tristate "MXC LDB" depends on FB_MXC_SYNC_PANEL diff --git a/drivers/video/fbdev/mxc/Makefile b/drivers/video/fbdev/mxc/Makefile index 58a889ba97af..922f98aed665 100644 --- a/drivers/video/fbdev/mxc/Makefile +++ b/drivers/video/fbdev/mxc/Makefile @@ -2,6 +2,8 @@ obj-y += mxc_dispdrv.o obj-$(CONFIG_FB_MXC_MIPI_DSI) += mipi_dsi.o obj-$(CONFIG_FB_MXC_MIPI_DSI_SAMSUNG) += mipi_dsi_samsung.o obj-$(CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL) += mxcfb_hx8369_wvga.o +obj-$(CONFIG_FB_MXC_TRULY_PANEL_TFT3P5079E) += mxcfb_otm8018b_wvga.o +obj-$(CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E) += mxcfb_hx8363_wvga.o obj-$(CONFIG_FB_MXC_LDB) += ldb.o obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o diff --git a/drivers/video/fbdev/mxc/mipi_dsi.h b/drivers/video/fbdev/mxc/mipi_dsi.h index 722ac6c2066b..1f8db555e58f 100644 --- a/drivers/video/fbdev/mxc/mipi_dsi.h +++ b/drivers/video/fbdev/mxc/mipi_dsi.h @@ -22,7 +22,7 @@ #define mipi_dbg(fmt, ...) #endif -#define DSI_CMD_BUF_MAXSIZE (32) +#define DSI_CMD_BUF_MAXSIZE (128) /* DPI interface pixel color coding map */ enum mipi_dsi_dpi_fmt { @@ -99,6 +99,16 @@ void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size, struct mipi_lcd_config **data); int mipid_hx8369_lcd_setup(struct mipi_dsi_info *); #endif +#ifdef CONFIG_FB_MXC_TRULY_PANEL_TFT3P5079E +void mipid_otm8018b_get_lcd_videomode(struct fb_videomode **mode, int *size, + struct mipi_lcd_config **data); +int mipid_otm8018b_lcd_setup(struct mipi_dsi_info *); +#endif +#ifdef CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E +void mipid_hx8363_get_lcd_videomode(struct fb_videomode **mode, int *size, + struct mipi_lcd_config **data); +int mipid_hx8363_lcd_setup(struct mipi_dsi_info *); +#endif #ifndef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL #error "Please configure MIPI LCD panel, we cannot find one!" diff --git a/drivers/video/fbdev/mxc/mipi_dsi_samsung.c b/drivers/video/fbdev/mxc/mipi_dsi_samsung.c index 553c0e83a7ea..7de2e2455665 100644 --- a/drivers/video/fbdev/mxc/mipi_dsi_samsung.c +++ b/drivers/video/fbdev/mxc/mipi_dsi_samsung.c @@ -56,6 +56,18 @@ static struct mipi_dsi_match_lcd mipi_dsi_lcd_db[] = { {mipid_hx8369_get_lcd_videomode, mipid_hx8369_lcd_setup} }, #endif +#ifdef CONFIG_FB_MXC_TRULY_PANEL_TFT3P5079E + { + "TRULY-WVGA-TFT3P5079E", + {mipid_otm8018b_get_lcd_videomode, mipid_otm8018b_lcd_setup} + }, +#endif +#ifdef CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E + { + "TRULY-WVGA-TFT3P5581E", + {mipid_hx8363_get_lcd_videomode, mipid_hx8363_lcd_setup} + }, +#endif { "", {NULL, NULL} } @@ -66,13 +78,18 @@ enum mipi_dsi_mode { DSI_VIDEO_MODE }; +enum mipi_dsi_trans_mode { + DSI_LP_MODE, + DSI_HS_MODE +}; + static struct regulator *mipi_phy_reg; static DECLARE_COMPLETION(dsi_rx_done); static DECLARE_COMPLETION(dsi_tx_done); static void mipi_dsi_dphy_power_down(void); static void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi, - enum mipi_dsi_mode mode); + enum mipi_dsi_trans_mode mode); static int mipi_dsi_lcd_init(struct mipi_dsi_info *mipi_dsi, struct mxc_dispdrv_setting *setting) @@ -214,6 +231,7 @@ static int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi_dsi, return -ETIMEDOUT; } } + mdelay(10); return 0; } @@ -374,9 +392,13 @@ static int mipi_dsi_master_init(struct mipi_dsi_info *mipi_dsi, MIPI_DSI_PLL_BYPASS(0) | MIPI_DSI_BYTE_CLK_SRC(0), mipi_dsi->mmio_base + MIPI_DSI_CLKCTRL); - writel(MIPI_DSI_PLL_EN(1) | - MIPI_DSI_PMS(0x4190), - mipi_dsi->mmio_base + MIPI_DSI_PLLCTRL); + if (!strcmp(mipi_dsi->lcd_panel, "TRULY-WVGA-TFT3P5581E")) + writel(MIPI_DSI_PLL_EN(1) | MIPI_DSI_PMS(0x3141), + mipi_dsi->mmio_base + MIPI_DSI_PLLCTRL); + else + writel(MIPI_DSI_PLL_EN(1) | MIPI_DSI_PMS(0x4190), + mipi_dsi->mmio_base + MIPI_DSI_PLLCTRL); + /* set PLLTMR: stable time */ writel(33024, mipi_dsi->mmio_base + MIPI_DSI_PLLTMR); udelay(300); @@ -392,17 +414,6 @@ static int mipi_dsi_master_init(struct mipi_dsi_info *mipi_dsi, reg |= MIPI_DSI_ESC_CLK_EN(1); writel(reg, mipi_dsi->mmio_base + MIPI_DSI_CLKCTRL); - /* check clock and data lanes are in stop state - * which means dphy is in low power mode - */ - while (!mipi_dsi_lane_stop_state(mipi_dsi)) { - time_out--; - if (time_out == 0) { - dev_err(dev, "MIPI DSI is not stop state.\n"); - return -EINVAL; - } - } - /* set main display resolution */ writel(MIPI_DSI_MAIN_HRESOL(mode->xres) | MIPI_DSI_MAIN_VRESOL(mode->yres) | @@ -412,8 +423,8 @@ static int mipi_dsi_master_init(struct mipi_dsi_info *mipi_dsi, /* set config register */ writel(MIPI_DSI_MFLUSH_VS(1) | MIPI_DSI_SYNC_IN_FORM(0) | - MIPI_DSI_BURST_MODE(0) | - MIPI_DSI_VIDEO_MODE(0) | + MIPI_DSI_BURST_MODE(1) | + MIPI_DSI_VIDEO_MODE(1) | MIPI_DSI_AUTO_MODE(0) | MIPI_DSI_HSE_DISABLE_MODE(0) | MIPI_DSI_HFP_DISABLE_MODE(0) | @@ -442,17 +453,31 @@ static int mipi_dsi_master_init(struct mipi_dsi_info *mipi_dsi, mipi_dsi->mmio_base + MIPI_DSI_MSYNC); /* configure d-phy timings */ - writel(MIPI_DSI_M_TLPXCTL(11) | MIPI_DSI_M_THSEXITCTL(18), - mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING); - writel(MIPI_DSI_M_TCLKPRPRCTL(13) | - MIPI_DSI_M_TCLKZEROCTL(65) | - MIPI_DSI_M_TCLKPOSTCTL(17) | - MIPI_DSI_M_TCLKTRAILCTL(13), - mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING1); - writel(MIPI_DSI_M_THSPRPRCTL(16) | - MIPI_DSI_M_THSZEROCTL(24) | - MIPI_DSI_M_THSTRAILCTL(16), - mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING2); + if (!strcmp(mipi_dsi->lcd_panel, "TRULY-WVGA-TFT3P5581E")) { + writel(MIPI_DSI_M_TLPXCTL(2) | MIPI_DSI_M_THSEXITCTL(4), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING); + writel(MIPI_DSI_M_TCLKPRPRCTL(5) | + MIPI_DSI_M_TCLKZEROCTL(14) | + MIPI_DSI_M_TCLKPOSTCTL(8) | + MIPI_DSI_M_TCLKTRAILCTL(3), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING1); + writel(MIPI_DSI_M_THSPRPRCTL(3) | + MIPI_DSI_M_THSZEROCTL(3) | + MIPI_DSI_M_THSTRAILCTL(3), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING2); + } else { + writel(MIPI_DSI_M_TLPXCTL(11) | MIPI_DSI_M_THSEXITCTL(18), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING); + writel(MIPI_DSI_M_TCLKPRPRCTL(13) | + MIPI_DSI_M_TCLKZEROCTL(65) | + MIPI_DSI_M_TCLKPOSTCTL(17) | + MIPI_DSI_M_TCLKTRAILCTL(13), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING1); + writel(MIPI_DSI_M_THSPRPRCTL(16) | + MIPI_DSI_M_THSZEROCTL(24) | + MIPI_DSI_M_THSTRAILCTL(16), + mipi_dsi->mmio_base + MIPI_DSI_PHYTIMING2); + } writel(0xf000f, mipi_dsi->mmio_base + MIPI_DSI_TIMEOUT); @@ -461,6 +486,20 @@ static int mipi_dsi_master_init(struct mipi_dsi_info *mipi_dsi, udelay(300); writel(0x1f, mipi_dsi->mmio_base + MIPI_DSI_FIFOCTRL); + /* check clock and data lanes are in stop state + * which means dphy is in low power mode + */ + while (!mipi_dsi_lane_stop_state(mipi_dsi)) { + time_out--; + if (time_out == 0) { + dev_err(dev, "MIPI DSI is not stop state.\n"); + return -EINVAL; + } + } + + /* transfer commands always in lp mode */ + writel(MIPI_DSI_CMD_LPDT, mipi_dsi->mmio_base + MIPI_DSI_ESCMODE); + mipi_dsi_init_interrupt(mipi_dsi); return 0; @@ -496,23 +535,17 @@ static void mipi_dsi_disp_deinit(struct mxc_dispdrv_handle *disp) } static void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi, - enum mipi_dsi_mode mode) + enum mipi_dsi_trans_mode mode) { - unsigned int dsi_config, escape_mode, dsi_clkctrl; + unsigned int dsi_clkctrl; - dsi_config = readl(mipi_dsi->mmio_base + MIPI_DSI_CONFIG); - escape_mode = readl(mipi_dsi->mmio_base + MIPI_DSI_ESCMODE); dsi_clkctrl = readl(mipi_dsi->mmio_base + MIPI_DSI_CLKCTRL); switch (mode) { - case DSI_COMMAND_MODE: - dsi_config &= ~MIPI_DSI_VIDEO_MODE(1); - escape_mode |= (MIPI_DSI_CMD_LPDT | MIPI_DSI_TX_LPDT); + case DSI_LP_MODE: dsi_clkctrl &= ~MIPI_DSI_TX_REQUEST_HSCLK(1); break; - case DSI_VIDEO_MODE: - dsi_config |= (MIPI_DSI_VIDEO_MODE(1) | MIPI_DSI_BURST_MODE(1)); - escape_mode &= ~(MIPI_DSI_CMD_LPDT | MIPI_DSI_TX_LPDT); + case DSI_HS_MODE: dsi_clkctrl |= MIPI_DSI_TX_REQUEST_HSCLK(1); break; default: @@ -521,10 +554,8 @@ static void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi, return; } - writel(escape_mode, mipi_dsi->mmio_base + MIPI_DSI_ESCMODE); - writel(dsi_config, mipi_dsi->mmio_base + MIPI_DSI_CONFIG); - writel(dsi_clkctrl, mipi_dsi->mmio_base + MIPI_DSI_CLKCTRL); + mdelay(1); } static int mipi_dsi_enable(struct mxc_dispdrv_handle *disp, @@ -542,14 +573,6 @@ static int mipi_dsi_enable(struct mxc_dispdrv_handle *disp, return ret; } } - - ret = device_reset(&mipi_dsi->pdev->dev); - if (ret) { - dev_err(&mipi_dsi->pdev->dev, - "failed to reset device: %d\n", ret); - return -EINVAL; - } - msleep(120); } if (!mipi_dsi->dsi_power_on) @@ -568,10 +591,15 @@ static int mipi_dsi_enable(struct mxc_dispdrv_handle *disp, if (ret) return -EINVAL; - /* the mipi lcd panel should be config - * in the dsi command mode. - */ - mipi_dsi_set_mode(mipi_dsi, DSI_COMMAND_MODE); + msleep(20); + ret = device_reset(&mipi_dsi->pdev->dev); + if (ret) { + dev_err(&mipi_dsi->pdev->dev, "failed to reset device: %d\n", ret); + return -EINVAL; + } + msleep(120); + + /* the panel should be config under LP mode */ ret = mipi_dsi->lcd_callback->mipi_lcd_setup(mipi_dsi); if (ret < 0) { dev_err(&mipi_dsi->pdev->dev, @@ -580,8 +608,8 @@ static int mipi_dsi_enable(struct mxc_dispdrv_handle *disp, } mipi_dsi->lcd_inited = 1; - /* change to video mode for panel display */ - mipi_dsi_set_mode(mipi_dsi, DSI_VIDEO_MODE); + /* change to HS mode for panel display */ + mipi_dsi_set_mode(mipi_dsi, DSI_HS_MODE); } else { ret = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); @@ -775,12 +803,6 @@ static int mipi_dsi_probe(struct platform_device *pdev) } } - ret = device_reset(&pdev->dev); - if (ret) { - dev_err(&pdev->dev, "failed to reset device: %d\n", ret); - goto dev_reset_fail; - } - mipi_dsi->lcd_panel = kstrdup(lcd_panel, GFP_KERNEL); if (!mipi_dsi->lcd_panel) { dev_err(&pdev->dev, "failed to allocate lcd panel name\n"); @@ -810,7 +832,6 @@ static int mipi_dsi_probe(struct platform_device *pdev) dispdrv_reg_fail: kfree(mipi_dsi->lcd_panel); kstrdup_fail: -dev_reset_fail: if (mipi_dsi->disp_power_on) regulator_disable(mipi_dsi->disp_power_on); diff --git a/drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c b/drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c new file mode 100644 index 000000000000..be97e8104067 --- /dev/null +++ b/drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/console.h> +#include <linux/io.h> +#include <linux/bitops.h> +#include <linux/spinlock.h> +#include <linux/mipi_dsi.h> +#include <linux/mxcfb.h> +#include <linux/backlight.h> +#include <video/mipi_display.h> + +#include "mipi_dsi.h" + +#define HX8363_TWO_DATA_LANE (0x2) +#define HX8363_MAX_DPHY_CLK (800) +#define HX8363_CMD_GETHXID (0xF4) +#define HX8363_CMD_GETHXID_LEN (0x4) +#define HX8363_ID (0x84) +#define HX8363_ID_MASK (0xFF) + + +#define CHECK_RETCODE(ret) \ +do { \ + if (ret < 0) { \ + dev_err(&mipi_dsi->pdev->dev, \ + "%s ERR: ret:%d, line:%d.\n", \ + __func__, ret, __LINE__); \ + return ret; \ + } \ +} while (0) + +static void parse_variadic(int n, u8 *buf, ...) +{ + int i = 0; + va_list args; + + if (unlikely(!n)) return; + + va_start(args, buf); + + for (i = 0; i < n; i++) + buf[i + 1] = (u8)va_arg(args, int); + + va_end(args); +} + +#define TC358763_DCS_write_1A_nP(n, addr, ...) { \ + int err; \ + \ + buf[0] = addr; \ + parse_variadic(n, buf, ##__VA_ARGS__); \ + \ + if (n >= 2) \ + err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \ + MIPI_DSI_DCS_LONG_WRITE, (u32*)buf, n + 1); \ + else if (n == 1) \ + err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \ + MIPI_DSI_DCS_SHORT_WRITE_PARAM, (u32*)buf, 0); \ + else if (n == 0) \ + { \ + buf[1] = 0; \ + err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \ + MIPI_DSI_DCS_SHORT_WRITE, (u32*)buf, 0); \ + } \ + CHECK_RETCODE(err); \ +} + +#define TC358763_DCS_write_1A_0P(addr) \ + TC358763_DCS_write_1A_nP(0, addr) + +#define TC358763_DCS_write_1A_1P(addr, ...) \ + TC358763_DCS_write_1A_nP(1, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_2P(addr, ...) \ + TC358763_DCS_write_1A_nP(2, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_3P(addr, ...) \ + TC358763_DCS_write_1A_nP(3, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_5P(addr, ...) \ + TC358763_DCS_write_1A_nP(5, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_6P(addr, ...) \ + TC358763_DCS_write_1A_nP(6, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_7P(addr, ...) \ + TC358763_DCS_write_1A_nP(7, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_12P(addr, ...) \ + TC358763_DCS_write_1A_nP(12, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_13P(addr, ...) \ + TC358763_DCS_write_1A_nP(13, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_14P(addr, ...) \ + TC358763_DCS_write_1A_nP(14, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_19P(addr, ...) \ + TC358763_DCS_write_1A_nP(19, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_34P(addr, ...) \ + TC358763_DCS_write_1A_nP(34, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_127P(addr, ...) \ + TC358763_DCS_write_1A_nP(127, addr, __VA_ARGS__) + +static int hx8363bl_brightness; + +static struct fb_videomode truly_lcd_modedb[] = { + { + "TRUULY-WVGA", 50, 480, 854, 41042, + 40, 60, + 3, 3, + 8, 4, + FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, + 0, + }, +}; + +static struct mipi_lcd_config lcd_config = { + .virtual_ch = 0x0, + .data_lane_num = HX8363_TWO_DATA_LANE, + .max_phy_clk = HX8363_MAX_DPHY_CLK, + .dpi_fmt = MIPI_RGB888, +}; + +void mipid_hx8363_get_lcd_videomode(struct fb_videomode **mode, int *size, + struct mipi_lcd_config **data) +{ + *mode = &truly_lcd_modedb[0]; + *size = ARRAY_SIZE(truly_lcd_modedb); + *data = &lcd_config; +} + +int mipid_hx8363_lcd_setup(struct mipi_dsi_info *mipi_dsi) +{ + u8 buf[DSI_CMD_BUF_MAXSIZE]; + + dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD HX8363 setup.\n"); + + TC358763_DCS_write_1A_3P(0xB9,0xFF,0x83,0x63);/* SET password */ + + TC358763_DCS_write_1A_19P(0xB1,0x01,0x00,0x44,0x08,0x01,0x10,0x10,0x36, + 0x3E,0x1A,0x1A,0x40,0x12,0x00,0xE6,0xE6,0xE6,0xE6,0xE6);/* Set Power */ + TC358763_DCS_write_1A_2P(0xB2,0x08,0x03);/* Set DISP */ + TC358763_DCS_write_1A_7P(0xB4,0x02,0x18,0x9C,0x08,0x18,0x04,0x6C); + TC358763_DCS_write_1A_1P(0xB6,0x00);/* Set VCOM */ + TC358763_DCS_write_1A_1P(0xCC,0x0B);/* Set Panel */ + TC358763_DCS_write_1A_34P(0xE0,0x0E,0x15,0x19,0x30,0x31,0x3F,0x27,0x3C,0x88,0x8F,0xD1,0xD5,0xD7,0x16,0x16, + 0x0C,0x1E,0x0E,0x15,0x19,0x30,0x31,0x3F,0x27,0x3C,0x88,0x8F, + 0xD1,0xD5,0xD7,0x16,0x16,0x0C,0x1E); + mdelay(5); + + TC358763_DCS_write_1A_1P(0x3A,0x77);/* 24bit */ + TC358763_DCS_write_1A_14P(0xBA,0x11,0x00,0x56,0xC6,0x10,0x89,0xFF,0x0F,0x32,0x6E,0x04,0x07,0x9A,0x92); + TC358763_DCS_write_1A_0P(0x21); + + TC358763_DCS_write_1A_0P(0x11); + msleep(10); + + TC358763_DCS_write_1A_0P(0x29); + msleep(120); + + return 0; +} + +static int mipid_bl_update_status(struct backlight_device *bl) +{ + return 0; +} + +static int mipid_bl_get_brightness(struct backlight_device *bl) +{ + return hx8363bl_brightness; +} + +static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi) +{ + return 0; +} + +static const struct backlight_ops mipid_lcd_bl_ops = { + .update_status = mipid_bl_update_status, + .get_brightness = mipid_bl_get_brightness, + .check_fb = mipi_bl_check_fb, +}; diff --git a/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c b/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c new file mode 100644 index 000000000000..fa7db02f37f6 --- /dev/null +++ b/drivers/video/fbdev/mxc/mxcfb_otm8018b_wvga.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/console.h> +#include <linux/io.h> +#include <linux/bitops.h> +#include <linux/spinlock.h> +#include <linux/mipi_dsi.h> +#include <linux/mxcfb.h> +#include <linux/backlight.h> +#include <video/mipi_display.h> + +#include "mipi_dsi.h" + +#define OTM8018B_TWO_DATA_LANE (0x2) +#define OTM8018B_MAX_DPHY_CLK (800) + +#define CHECK_RETCODE(ret) \ +do { \ + if (ret < 0) { \ + dev_err(&mipi_dsi->pdev->dev, \ + "%s ERR: ret:%d, line:%d.\n", \ + __func__, ret, __LINE__); \ + return ret; \ + } \ +} while (0) + +static void parse_variadic(int n, u8 *buf, ...) +{ + int i = 0; + va_list args; + + if (unlikely(!n)) return; + + va_start(args, buf); + + for (i = 0; i < n; i++) + buf[i + 1] = (u8)va_arg(args, int); + + va_end(args); +} + +#define TC358763_DCS_write_1A_nP(n, addr, ...) { \ + int err; \ + \ + buf[0] = addr; \ + parse_variadic(n, buf, ##__VA_ARGS__); \ + \ + err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \ + MIPI_DSI_GENERIC_LONG_WRITE, (u32*)buf, n + 1); \ + CHECK_RETCODE(err); \ +} + +#define TC358763_DCS_write_1A_0P(addr) \ + TC358763_DCS_write_1A_nP(0, addr) + +#define TC358763_DCS_write_1A_1P(addr, ...) \ + TC358763_DCS_write_1A_nP(1, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_2P(addr, ...) \ + TC358763_DCS_write_1A_nP(2, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_3P(addr, ...) \ + TC358763_DCS_write_1A_nP(3, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_5P(addr, ...) \ + TC358763_DCS_write_1A_nP(5, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_6P(addr, ...) \ + TC358763_DCS_write_1A_nP(6, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_12P(addr, ...) \ + TC358763_DCS_write_1A_nP(12, addr, __VA_ARGS__) + +#define TC358763_DCS_write_1A_14P(addr, ...) \ + TC358763_DCS_write_1A_nP(14, addr, __VA_ARGS__) + +static int otm8018bbl_brightness; + +static struct fb_videomode truly_lcd_modedb[] = { + { + "TRULY-WVGA", 64, 480, 800, 37880, + 8, 8, + 6, 6, + 8, 6, + FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, + 0, + }, +}; + +static struct mipi_lcd_config lcd_config = { + .virtual_ch = 0x0, + .data_lane_num = OTM8018B_TWO_DATA_LANE, + .max_phy_clk = OTM8018B_MAX_DPHY_CLK, + .dpi_fmt = MIPI_RGB888, +}; + +void mipid_otm8018b_get_lcd_videomode(struct fb_videomode **mode, int *size, + struct mipi_lcd_config **data) +{ + *mode = &truly_lcd_modedb[0]; + *size = ARRAY_SIZE(truly_lcd_modedb); + *data = &lcd_config; +} + +int mipid_otm8018b_lcd_setup(struct mipi_dsi_info *mipi_dsi) +{ + u8 buf[DSI_CMD_BUF_MAXSIZE]; + + dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD setup.\n"); + + TC358763_DCS_write_1A_3P(0xFF,0x80,0x09,0x01); + TC358763_DCS_write_1A_1P(0x00,0x80); + TC358763_DCS_write_1A_2P(0xFF,0x80,0x09); + + TC358763_DCS_write_1A_1P(0x00,0x03); + TC358763_DCS_write_1A_1P(0xff,0x01); + + TC358763_DCS_write_1A_1P(0x00,0xb4); + TC358763_DCS_write_1A_1P(0xc0,0x10); + + TC358763_DCS_write_1A_1P(0x00,0x82); + TC358763_DCS_write_1A_1P(0xC5,0xa3); + + TC358763_DCS_write_1A_1P(0x00,0x90); + TC358763_DCS_write_1A_2P(0xC5,0x96,0x76); + + TC358763_DCS_write_1A_1P(0x00,0x00); + TC358763_DCS_write_1A_2P(0xD8,0x75,0x73); + + TC358763_DCS_write_1A_1P(0x00,0x00); + TC358763_DCS_write_1A_1P(0xD9,0x5e); + + TC358763_DCS_write_1A_1P(0x00,0x81); + TC358763_DCS_write_1A_1P(0xC1,0x66); + + TC358763_DCS_write_1A_1P(0x00,0xA1); + TC358763_DCS_write_1A_1P(0xC1,0x08); + + TC358763_DCS_write_1A_1P(0x00,0x89); + TC358763_DCS_write_1A_1P(0xC4,0x08); + + TC358763_DCS_write_1A_1P(0x00,0xA2); + TC358763_DCS_write_1A_3P(0xC0,0x1B,0x00,0x02); + + TC358763_DCS_write_1A_1P(0x00,0x81); + TC358763_DCS_write_1A_1P(0xC4,0x83); + + TC358763_DCS_write_1A_1P(0x00,0x92); + TC358763_DCS_write_1A_1P(0xC5,0x01); + + TC358763_DCS_write_1A_1P(0x00,0xb1); + TC358763_DCS_write_1A_1P(0xC5,0xa9); + + TC358763_DCS_write_1A_1P(0x00,0x90); + TC358763_DCS_write_1A_6P(0xC0,0x00,0x44,0x00,0x00,0x00,0x03); + + TC358763_DCS_write_1A_1P(0x00,0xA6); + TC358763_DCS_write_1A_3P(0xC1,0x00,0x00,0x00); + + TC358763_DCS_write_1A_1P(0x00,0x80); + TC358763_DCS_write_1A_12P(0xCE,0x87,0x03,0x00,0x85,0x03,0x00, + 0x86,0x03,0x00,0x84,0x03,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xA0); + TC358763_DCS_write_1A_14P(0xCE,0x38,0x03,0x03,0x58,0x00,0x00, + 0x00,0x38,0x02,0x03,0x59,0x00,0x00,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xB0); + TC358763_DCS_write_1A_14P(0xCE,0x38,0x01,0x03,0x5a,0x00,0x00, + 0x00,0x38,0x00,0x03,0x5b,0x00,0x00,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xC0); + TC358763_DCS_write_1A_14P(0xCE,0x30,0x00,0x03,0x5c,0x00,0x00, + 0x00,0x30,0x01,0x03,0x5d,0x00,0x00,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xD0); + TC358763_DCS_write_1A_14P(0xCE,0x30,0x02,0x03,0x5e,0x00,0x00, + 0x00,0x30,0x03,0x03,0x5f,0x00,0x00,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xC7); + TC358763_DCS_write_1A_1P(0xCF,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xC9); + TC358763_DCS_write_1A_1P(0xCF,0x00); + + TC358763_DCS_write_1A_1P(0x00,0xC4); + TC358763_DCS_write_1A_6P(0xCB,0x04,0x04,0x04,0x04,0x04,0x04); + + TC358763_DCS_write_1A_1P(0x00,0xd9); + TC358763_DCS_write_1A_6P(0xCB,0x04,0x04,0x04,0x04,0x04,0x04); + + TC358763_DCS_write_1A_1P(0x00,0x84); + TC358763_DCS_write_1A_6P(0xCc,0x0c,0x0a,0x10,0x0e,0x03,0x04); + + TC358763_DCS_write_1A_1P(0x00,0x9e); + TC358763_DCS_write_1A_1P(0xCc,0x0b); + + TC358763_DCS_write_1A_1P(0x00,0xA0); + TC358763_DCS_write_1A_5P(0xCC,0x09,0x0f,0x0d,0x01,0x02); + + TC358763_DCS_write_1A_1P(0x00,0xb4); + TC358763_DCS_write_1A_5P(0xCC,0x0d,0x09,0x0b,0x02,0x01); + + TC358763_DCS_write_1A_1P(0x00,0xce); + TC358763_DCS_write_1A_1P(0xCc,0x0e); + + TC358763_DCS_write_1A_1P(0x00,0xD0); + TC358763_DCS_write_1A_5P(0xCC,0x10,0x0a,0x0c,0x04,0x03); + + TC358763_DCS_write_1A_1P(0x00,0x00); + TC358763_DCS_write_1A_1P(0x3a,0x77); + + TC358763_DCS_write_1A_0P(0x11); + + msleep(200); + + TC358763_DCS_write_1A_0P(0x29); + + TC358763_DCS_write_1A_0P(0x2C); + + return 0; +} + +static int mipid_bl_update_status(struct backlight_device *bl) +{ + return 0; +} + +static int mipid_bl_get_brightness(struct backlight_device *bl) +{ + return otm8018bbl_brightness; +} + +static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi) +{ + return 0; +} + +static const struct backlight_ops mipid_lcd_bl_ops = { + .update_status = mipid_bl_update_status, + .get_brightness = mipid_bl_get_brightness, + .check_fb = mipi_bl_check_fb, +}; diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c index a50c35b48951..4e0fa2a1cc6d 100644 --- a/drivers/video/fbdev/mxsfb.c +++ b/drivers/video/fbdev/mxsfb.c @@ -44,6 +44,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/of_device.h> +#include <linux/of_gpio.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/interrupt.h> @@ -1384,11 +1385,23 @@ static int mxsfb_probe(struct platform_device *pdev) struct fb_info *fb_info; struct pinctrl *pinctrl; int irq = platform_get_irq(pdev, 0); - int ret; + int gpio, ret; if (of_id) pdev->id_entry = of_id->data; + gpio = of_get_named_gpio(pdev->dev.of_node, "enable-gpio", 0); + if (gpio == -EPROBE_DEFER) + return -EPROBE_DEFER; + + if (gpio_is_valid(gpio)) { + ret = devm_gpio_request_one(&pdev->dev, gpio, GPIOF_OUT_INIT_LOW, "lcd_pwr_en"); + if (ret) { + dev_err(&pdev->dev, "faild to request gpio %d, ret = %d\n", gpio, ret); + return ret; + } + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Cannot get memory IO resource\n"); |