diff options
author | Jason Chen <b02280@freescale.com> | 2009-12-17 18:58:56 +0800 |
---|---|---|
committer | Jason Chen <b02280@freescale.com> | 2009-12-17 20:51:17 +0800 |
commit | a0f08ff09d20a69e68eefcd14edb6354dfc46d98 (patch) | |
tree | 58e9e8ae96026106be0962d0c2aafeb17ff883a8 /drivers | |
parent | 520f070590696c4790f2d7feee6ae70fd132acf6 (diff) |
ENGR00119274 TVE: HDTV can not work
1.arrange display port according to choice of different display device
2.for ipu_disp.c: not round pixel clock to even for tvout.
3.cmdline "hdtv" enable 720P, "hdtv=2" enable 720P as primary.
Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mxc/ipu3/ipu_disp.c | 33 | ||||
-rw-r--r-- | drivers/video/mxc/mxc_ipuv3_fb.c | 2 | ||||
-rw-r--r-- | drivers/video/mxc/tve.c | 20 |
3 files changed, 32 insertions, 23 deletions
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index 035d0c9e4519..d7cc2107046e 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -56,6 +56,7 @@ struct dp_csc_param_t { int dmfc_type_setup; static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; +int g_di1_tvout; void _ipu_dmfc_init(int dmfc_type, int first) { @@ -965,21 +966,23 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); if (sig.ext_clk) { - /* Set the PLL to be an even multiple of the pixel clock. */ - if ((clk_get_usecount(g_pixel_clk[0]) == 0) && - (clk_get_usecount(g_pixel_clk[1]) == 0)) { - di_parent = clk_get_parent(g_di_clk[disp]); - rounded_pixel_clk = - clk_round_rate(g_pixel_clk[disp], pixel_clk); - div = clk_get_rate(di_parent) / rounded_pixel_clk; - if (div % 2) - div++; - - if (clk_get_rate(di_parent) != div * rounded_pixel_clk) - clk_set_rate(di_parent, div * rounded_pixel_clk); - msleep(10); - clk_set_rate(g_di_clk[disp], 2 * rounded_pixel_clk); - msleep(10); + if (!(g_di1_tvout && (disp == 1))) { /* not round div for tvout*/ + /* Set the PLL to be an even multiple of the pixel clock. */ + if ((clk_get_usecount(g_pixel_clk[0]) == 0) && + (clk_get_usecount(g_pixel_clk[1]) == 0)) { + di_parent = clk_get_parent(g_di_clk[disp]); + rounded_pixel_clk = + clk_round_rate(g_pixel_clk[disp], pixel_clk); + div = clk_get_rate(di_parent) / rounded_pixel_clk; + if (div % 2) + div++; + + if (clk_get_rate(di_parent) != div * rounded_pixel_clk) + clk_set_rate(di_parent, div * rounded_pixel_clk); + msleep(10); + clk_set_rate(g_di_clk[disp], 2 * rounded_pixel_clk); + msleep(10); + } } clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); } else { diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index f9b8f6b0f84c..39c9fdd207af 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -168,6 +168,8 @@ static int _setup_disp_channel1(struct fb_info *fbi) if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) { fbi->var.vmode = registered_fb[i]->var.vmode; + mxc_fbi->ipu_di_pix_fmt = + mxc_fbi_tmp->ipu_di_pix_fmt; break; } } diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c index 061d65a7cd20..74c98521bfc1 100644 --- a/drivers/video/mxc/tve.c +++ b/drivers/video/mxc/tve.c @@ -221,8 +221,8 @@ static int tve_setup(int mode) { u32 reg; struct clk *pll3_clk; - unsigned long pll3_clock_rate = 216000000; - struct clk *ipu_di0_clk; + unsigned long pll3_clock_rate = 216000000, di1_clock_rate = 27000000; + struct clk *ipu_di1_clk; if (tve.cur_mode == mode) return 0; @@ -233,25 +233,23 @@ static int tve_setup(int mode) case TVOUT_FMT_PAL: case TVOUT_FMT_NTSC: pll3_clock_rate = 216000000; + di1_clock_rate = 27000000; break; case TVOUT_FMT_720P60: pll3_clock_rate = 297000000; + di1_clock_rate = 74250000; break; } if (enabled) clk_disable(tve.clk); pll3_clk = clk_get(NULL, "pll3"); - ipu_di0_clk = clk_get(NULL, "ipu_di0_clk"); - if ((clk_get_parent(ipu_di0_clk) == pll3_clk) && - (clk_get_rate(pll3_clk) != pll3_clock_rate)) { - printk(KERN_INFO "Cannot setup TV since display is using PLL3\n"); - return -EINVAL; - } + ipu_di1_clk = clk_get(NULL, "ipu_di1_clk"); clk_disable(pll3_clk); clk_set_rate(pll3_clk, pll3_clock_rate); clk_enable(pll3_clk); + clk_set_rate(ipu_di1_clk, di1_clock_rate); clk_enable(tve.clk); @@ -616,6 +614,7 @@ static int _tve_get_revision(void) return rev; } +extern int g_di1_tvout; static int tve_probe(struct platform_device *pdev) { int ret, i; @@ -623,6 +622,11 @@ static int tve_probe(struct platform_device *pdev) struct tve_platform_data *plat_data = pdev->dev.platform_data; u32 conf_reg; + if (!g_di1_tvout) { + pr_debug("TVE: DI1 was occupied by other device,TVE will not enable\n"); + return -EBUSY; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) return -ENOMEM; |